'!! ! 0 ! ,'&$% ! " (/#% %$!'"( $% SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 FEATURES D 24-Bit Resolution D Analog Performance: D D D D D D D D D D D − Dynamic Range: 113 dB − THD+N: 0.001% − Full-Scale Output: 2.1 V RMS (at Postamp) Differential Voltage Output: 3.2 Vp-p 8× Oversampling Digital Filter: − Stop-Band Attenuation: –82 dB − Pass-Band Ripple: ±0.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING PCM1791ADB 28-lead SSOP 28DB −25°C to 85°C PCM1791A ORDERING NUMBER TRANSPORT MEDIA PCM1791ADB Tube PCM1791ADBR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM1791A Supply voltage VCCF, VCCL, VCCC, VCCR VDD −0.3 V to 6.5 V −0.3 V to 4 V ±0.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1791ADB PARAMETER TEST CONDITIONS MIN TYP UNIT MAX DIGITAL FILTER PERFORMANCE ±0.1 De-emphasis error dB FILTER CHARACTERISTICS-1: SHARP ROLL OFF Pass band ±0.002 dB 0.454 fS –3 dB Stop band 0.49 fS 0.546 fS ±0.
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www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 TYPICAL PERFORMANCE CURVES DIGITAL FILTER Digital Filter Response AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 3 0.003 −20 2 0.002 Amplitude − dB Amplitude − dB −40 −60 −80 −100 1 0.001 0 −1 −0.001 −120 −2 −0.002 −140 −160 0 1 2 3 −3 −0.003 0.0 4 0.1 Frequency [× fS] 0.2 0.3 0.4 0.5 Frequency [× fS] Figure 1. Frequency Response, Sharp Rolloff Figure 2.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 De-Emphasis Filter DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 32 kHz −1 0.3 De-Emphasis Error − dB −2 De-Emphasis Level − dB fS = 32 kHz 0.4 −3 −4 −5 −6 −7 0.2 0.1 −0.0 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 0 2 4 f − Frequency − kHz Figure 5 8 10 12 14 Figure 6 DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 44.1 kHz −1 fS = 44.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 De-Emphasis Filter (Continued) DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 0.5 fS = 48 kHz −1 0.3 De-Emphasis Error − dB De-Emphasis Level − dB −2 −3 −4 −5 −6 −7 0.2 0.1 −0.0 0.0 −0.1 −0.2 −8 −0.3 −9 −0.4 −10 −0.5 0 2 4 6 8 10 12 14 f − Frequency − kHz Figure 9 10 fS = 48 kHz 0.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 118 116 fS = 192 kHz Dynamic Range − dB THD+N − Total Harmonic Distortion + Noise − % 0.01 fS = 96 kHz 0.001 fS = 44.1 kHz fS = 44.1 kHz 112 fS = 192 kHz 110 0.0001 4.00 4.25 4.50 4.75 5.00 5.25 108 4.00 4.25 4.50 5.50 5.75 6.00 VCC − Supply Voltage − V 4.75 5.00 5.25 5.50 5.75 6.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 118 116 fS = 192 kHz Dynamic Range − dB THD+N − Total Harmonic Distortion + Noise − % 0.01 fS = 96 kHz 0.001 fS = 44.1 kHz fS = 96 kHz fS = 44.1 kHz 114 fS = 192 kHz 112 110 0.0001 −50 −25 0 25 50 75 108 −50 100 TA − Free-Air Temperature − °C −25 Figure 15 116 112 fS = 44.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY −50 −60 −60 −70 −70 −80 −80 −90 −90 Amplitude − dB Amplitude − dB AMPLITUDE vs FREQUENCY −50 −100 −110 −120 −100 −110 −120 −130 −130 −140 −140 −150 −150 −160 −160 0 5 10 15 20 0 10 20 30 f − Frequency − kHz 40 50 60 70 80 90 100 f − Frequency − kHz Figure 19. −60-dB Output Spectrum, BW = 20 kHz Figure 20. −60-dB Output Spectrum, BW = 100 kHz NOTE: PCM mode, fS = 44.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY −50 −60 −70 Amplitude − dB −80 −90 −100 −110 −120 −130 −140 −150 −160 0 5 10 15 20 f − Frequency − kHz Figure 22. −60-dB Output Spectrum, DSD Mode TOTAL HARMONIC DISTORTION + NOISE vs INPUT LEVEL THD+N − Total Harmonic Distortion + Noise − % 100 10 1 0.1 0.01 0.001 0.0001 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Input Level − dBFS Figure 23.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM1791A requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 5). The PCM1791A has a system clock detection circuit that automatically senses which frequency the system clock is operating. Table 1 shows examples of system clock frequencies for common audio sampling rates.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 VDD 2.4 V (Max) 2 V (Typ) 1.6 V (Min) Reset Reset Removal Internal Reset 1024 System Clocks System Clock Figure 25. Power-On Reset Timing RST (Pin 6) 1.4 V t(RST) Reset Reset Removal Internal Reset 1024 System Clocks System Clock t(RST) PARAMETERS MIN Reset pulse duration, LOW 20 Figure 26.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 AUDIO DATA INTERFACE Audio Serial Interface The audio interface port is a 3-wire serial port. It includes LRCK (pin 1), BCK (pin 2), and DATA (pin 3). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1791A on the rising edge of BCK. LRCK is the serial audio left/right word clock.
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www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 External Digital Filter Interface and Timing The PCM1791A supports an external digital filter interface comprising a 4-wire synchronous serial port, which allows the use of an external digital filter. External filters include the Texas Instruments DF1704 and DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 FUNCTION DESCRIPTIONS Zero Detect The PCM1791A has a zero-detect function. When the PCM1791A detects the zero conditions as shown in Table 2, the PCM1791A sets ZEROL (pin 23) and ZEROR (pin 22) to HIGH. Table 2. Zero Conditions MODE DETECTING CONDITION AND TIME PCM DATA is continuously LOW for 1024 LRCKs. External DF mode DSD DATA is continuously LOW for 1024 WDCKs.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 MS MC MDI R/W A6 A5 A4 A3 A2 A1 A0 High Impedance MDO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 When Read Mode is Instructed NOTE: Bit 15 is used for selection of write or read. Setting R/W = 0 indicates a write, while R/W = 1 indicates a read. Bits 14−8 are used for the register address. Bits 7–0 are used for register data. Figure 30. Serial Control Format t(MHH) MS 1.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 I2C Interface The PCM1791A supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave device. This protocol is explained in I2C specification 2.0. In I2C mode, the control terminals are changed as follows.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Write Register A master can write to any PCM1791A registers using single or multiple accesses. The master sends a PCM1791A slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented automatically by 1.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Case 2: 1. t(SCK) > 120 ns 2. t(S−HD) or t(RS−HD) < t(SCK) × 5 3. Spike noise exists on both SCL and SDA during the hold time. SCL Noise SDA When these conditions occur at the same time, the PCM1791A fails to detect a start condition. Case 3: 1. t(SCK) < 50 ns 2. t(SP) > t(SCK) 3. Spike noise exists on SCL just after SCL goes LOW. 4. Spike noise exists on SDA just before SCL goes LOW.
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www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM1791A includes a number of user-programmable functions which are accessed via mode control registers. The registers are programmed using the serial control interface, which was previously discussed in this data sheet. Table 3 lists the available mode-control functions, along with their default reset conditions and associated register index. Table 3.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Register Map The mode control register map is shown in Table 4. Registers 16–21 include an R/W bit, which determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only. Table 4.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Register 18 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 R/W 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 B3 B2 DMF1 DMF0 B1 B0 DME MUTE R/W: Read/Write Mode Select When R/W = 0, a write operaton is performed. When R/W = 1, a read operaton is performed. Default value: 0 ATLD: Attenuation Load Control This bit is available for read and write.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 DME: Digital De-Emphasis Control This bit is available for read and write. Default value: 0 DME = 0 De-emphasis disabled (default) DME = 1 De-emphasis enabled The DME bit enables or disables the de-emphasis function for both channels. MUTE: Soft Mute Control This bit is available for read and write.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 OPE: DAC Operation Control This bit is available for read and write. Default value: 0 OPE = 0 DAC operation enabled (default) OPE = 1 DAC operation disabled The OPE bit enables or disables the analog output for both channels. Disabling the analog outputs forces them to the bipolar zero level (BPZ) even if digital audio data is present on the input. FLT: Digital Filter Rolloff Control This bit is available for read and write.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 DFTH: Digital Filter Bypass (or Through Mode) Control This bit is available for read and write. Default value: 0 DFTH = 0 Digital filter enabled (default) DFTH = 1 Digital filter bypassed for the external digital filter The DFTH bit enables or disables the external digital filter interface mode. MONO: Monaural Mode Selection This bit is available for read and write.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 DZ[1:0]: DSD Zero Output Enable These bits are available for read and write. Default value: 00 Zero Output Enable DZ[1:0] 00 Disabled (default) 01 Even pattern detect 1x 96H pattern detect The DZ bits enable or disable the output zero flags, and select the zero pattern in the DSD mode. PCMZ: PCM Zero Output Enable This bit is available for read and write.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 TYPICAL CONNECTION DIAGRAM IN PCM MODE L/R Clock (fS) 1 LRCK MS 28 Bit Clock 2 BCK MC 27 Audio Data 3 DATA MDI 26 4 MUTE MDO 25 5 SCK MSEL 24 6 RST ZEROL 23 7 VDD ZEROR 22 System Clock 3.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 APPLICATION INFORMATION ANALOG OUTPUTS 1 LRCK MS 28 2 BCK MC 27 3 DATA MDI 26 4 MUTE MDO 25 5 SCK MSEL 24 6 RST ZEROL 23 7 VDD ZEROR 22 PCM1791A 8 DGND VCCF 21 9 AGNDF VCCL 20 AGNDL 19 11 AGNDR VOUTL– 18 12 VOUTR– VOUTL+ 17 10 VCCR 13 VOUTR+ 14 VCOM + AGNDC 16 VCCC 15 0.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Analog Gain of Balanced Amplifier The DAC voltage outputs are followed by balanced amplifier stages, which sum the differential signals for each channel, creating a single-ended voltage output. In addition, the balanced amplifiers provide a third-order low-pass filter function, which band limits the audio output signal. The cutoff frequency and gain are determined by external R and C component values.
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www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Audio Format The PCM1791A in the external digital filter interface mode supports right-justified audio formats including 16-bit, 20-bit, and 24-bit audio data, as shown in Figure 39. The audio format is selected by the FMT[2:0] bits of control register 18.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Functions Available in the External Digital Filter Mode The external digital filter mode allows access to the majority of the PCM1791A mode control functions. The following table shows the register mapping available when the external digital filter mode is selected, along with descriptions of functions which are modified when using this mode selection.
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www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Pin Assignments When Using the DSD Format Interface Several pins are redefined for DSD mode operation. These include: D D D D DATA (pin 3): DSDL as L-channel DSD data input, or as DSD data input in mono mode LRCK (pin 1): DSDR as R-channel DSD data input SCK (pin 5): DBCK as bit clock for DSD data BCK (pin 2): Set LOW (N/A) Requirements for System Clock The bit clock (DBCK) for DSD mode is required at pin 5 of the PCM1791A.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 ANALOG FIR FILTER PERFORMANCE IN DSD MODE GAIN vs FREQUENCY GAIN vs FREQUENCY 0 0 −1 −10 −2 −20 Gain − dB Gain − dB fc = 185 kHz Gain(1) = −6.6 dB −3 −30 −4 −40 −5 −50 −6 −60 0 50 100 150 200 0 f − Frequency − kHz 500 1000 1500 f − Frequency − kHz Figure 44. DSD Filter-1, Low BW Figure 45.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 ANALOG FIR FILTER PERFORMANCE IN DSD MODE (CONTINUED) GAIN vs FREQUENCY GAIN vs FREQUENCY 0 0 −1 −10 −2 −20 Gain − dB Gain − dB fc = 85 kHz Gain(1) = −1.5 dB −3 −30 −4 −40 −5 −50 −60 −6 0 50 100 150 0 200 500 1000 1500 f − Frequency − kHz f − Frequency − kHz Figure 48. DSD Filter-3, Low BW Figure 49.
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www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 TDMCA INTERFACE FORMAT The PCM1791A supports the time-division-multiplexed command and audio (TDMCA) data format to simplify the host control serial interface. The TDMCA format is designed not only for the McBSP of TI DSPs but also for any programmable devices. The TDMCA format can transfer not only audio data but also command data, so that it can be used together with any kind of device that supports the TDMCA format.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Device ID Determination The TDMCA mode also supports a multichip implementation in one system. This means a host controller (DSP) can simultaneously support several TDMCA devices, which can be of the same type or different types, including PCM devices. The PCM devices are categorized as IN device, OUT device, IN/OUT device, and NO device.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 DCII LRCK BCK IN/OUT DCOI Device (DIX1700) DI DCIO DO DCOO Device ID = 1 LRCK BCK IN Device (PCM1791A) DI DO LRCK DCI DCO Device ID = 2 NO Device DCI BCK DI DO DCO Device ID = 3 • • • FSX FSR CLKX CLKR DX DR LRCK OUT Device DCI BCK DI DO DCO Device ID = 2 TI DSP LRCK OUT Device DCI BCK DI DO DCO Device ID = 3 • • • Figure 54.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 LRCK BCK DID DI Device ID = 1 DCO1 Device ID = 2 DCO1 DCI2 Command Field Device ID = 3 DCO2 DCI3 • • • • • • Device ID = 30 DCO29 DCI30 58 BCK Figure 55. Device ID Determination Sequence TDMCA Frame In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields. All of them are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each field.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 1/fS (256 BCK Clocks) 7 Packets × 32 Bits LRCK BCK DI Ch1 CMD Ch2 Ch3 Ch4 Ch5 Ch6 Don’t Care CMD IN and OUT Channel Orders are Completely Independent DO Ch1 CMD Ch2 Figure 57. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read Command Field The normal command field is defined as follows.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Audio Fields The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed with 0s as shown in the following example. audio data 31 16 MSB 24 bits 12 8 7 LSB 4 3 0 All 0s TDMCA Register Requirements TDMCA mode requires device ID and audio channel information, previously described.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 1/fS (384 BCK Clocks) 9 Packets × 32 Bits LRCK BCK IN Daisy Chain CMD DI Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Don’t Care CMD DCI1 DID = 1 DID = 2 DID = 3 DID = 4 DCO1 DCI2 DCO2 DCI3 DCO3 DCI4 DCO4 Figure 59. DCO Output Timing of TDMCA Mode Operation If some devices are skipped due to no active audio channel, the skipped devices must notify the next device that the DCO will be passed through the next DCI.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Command Packet LRCK BCK DI DID EMD DCO1 DCO2 • • • Figure 61.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 LRCK t(LB) t(BL) BCK t(BCY) t(DS) t(DH) DI t(DOE) DO t(DS) t(DH) DCI t(COE) DCO PARAMETER t(BCY) BCK pulse cycle time t(LB) LRCK setup time MIN MAX UNITS 20 ns 0 ns t(BL) t(DS) LRCK hold time 3 ns DI setup time 0 ns t(DH) t(DS) DI hold time 3 ns DCI setup time 0 ns 3 ns t(DH) DCI hold time t(DOE) DO output delay(1) t(COE) DCO output delay(1) (1) Load capacitance is 10 pF. Figure 62.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 THEORY OF OPERATION Upper 6 Bit ICOB Decoder 0−62 Level 0−66 Digital Input 24 Bit 8 fS MSB and Lower 18 Bit 3rd-Order 5-Level Sigma-Delta Advanced DWA Current Segment DAC I/V Converter Analog Voltage Output 0−4 Level Figure 63. Advanced Segment DAC With I/V Converter The PCM1791A uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 CONSIDERATIONS FOR APPLICATION CIRCUITS PCB Layout Guidelines A typical PCB floor plan for the PCM1791A is shown in Figure 64. A ground plane is recommended, with the analog and digital sections being isolated from one another using a split or cut in the circuit board.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 Power Supplies RF Choke or Ferrite Bead +5V AGND +VS −VS REG VCC VDD VDD DGND Output Circuits PCM1791A AGND Digital Section Analog Section Common Ground Figure 65. Single-Supply PCB Layout Bypass and Decoupling Capacitor Requirements Various sized decoupling capacitors can be used, with no special tolerances being required.
www.ti.com SLES071B − MARCH 2003 − REVISED NOVEMBER 2006 MECHANICAL DATA DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 5,60 5,00 8,20 7,40 Gage Plane 1 14 0,25 A 0°−ā 8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1791ADBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.5 10.8 2.4 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1791ADBR SSOP DB 28 2000 336.6 336.6 28.
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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