'!! ! 0 ! ,'&$% ! " (/#% %$!'"( $% SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 FEATURES D 24-Bit Resolution D Analog Performance: − Dynamic Range: − 132 dB (9 V rms, Mono) − 129 dB (4.5 V rms, Stereo) − 127 dB (2 V rms, Stereo) − THD+N: 0.0004% D Differential Current Output: 7.8 mA p-p D 8× Oversampling Digital Filter: − Stop-Band Attenuation: –130 dB − Pass-Band Ripple: ±0.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING PCM1792ADB 28-lead SSOP 28DB −25°C to 85°C PCM1792A ORDERING NUMBER TRANSPORT MEDIA PCM1792ADB Tube PCM1792ADBR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM1792A VCC1, VCC2L, VCC2R VDD Supply voltage −0.3 V to 6.5 V −0.3 V to 4 V ±0.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PCM1792ADB PARAMETER TEST CONDITIONS MIN TYP MAX fS = 44.1 kHz fS = 96 kHz 0.0004% 0.0008% fS = 192 kHz EIAJ, A-weighted, fS = 44.1 kHz 0.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PCM1792ADB PARAMETER TEST CONDITIONS MIN TYP UNIT MAX DSD MODE DYNAMIC PERFORMANCE (1) (2) (44.1 kHz, 64 fS) THD+N at FS 4.5 V rms Dynamic range –60 dB, EIAJ, A-weighted 0.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data unless otherwise noted PCM1792ADB PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY REQUIREMENTS VDD VCC1 VCC2L 3 3.3 3.6 Vdc 4.75 5 5.25 Vdc fS = 44.1 kHz fS = 96 kHz 12 15 fS = 192 kHz fS = 44.1 kHz 45 fS = 96 kHz fS = 192 kHz 35 fS = 44.
www.ti.
www.ti.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 TYPICAL PERFORMANCE CURVES DIGITAL FILTER Digital Filter Response AMPLITUDE vs FREQUENCY 0 2 0.00002 −50 1 0.00001 −100 Amplitude − dB Amplitude − dB AMPLITUDE vs FREQUENCY −150 −1 −0.00001 −200 0 1 2 3 4 0 −2 −0.00002 0.0 0.1 Frequency [× fS] 0.2 0.3 0.4 0.5 Frequency [× fS] Figure 1. Frequency Response, Sharp Rolloff Figure 2.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 De-Emphasis Filter DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 20 fS = 32 kHz fS = 32 kHz 15 0.015 De-Emphasis Error − dB De-Emphasis Level − dB −2 −4 −6 10 0.010 5 0.005 0 −5 −0.005 −10 −0.010 −8 −15 −0.015 −10 −20 −0.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 De-Emphasis Filter (Continued) DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 20 0.020 fS = 48 kHz fS = 48 kHz 15 0.015 De-Emphasis Error − dB De-Emphasis Level − dB −2 −4 −6 10 0.010 5 0.005 0 −5 −0.005 −10 −0.010 −8 −15 −0.015 −10 −20 −0.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 132 130 fS = 96 kHz Dynamic Range − dB THD+N − Total Harmonic Distortion + Noise − % 0.01 fS = 192 kHz 0.001 fS = 96 kHz fS = 48 kHz 128 fS = 192 kHz 126 124 fS = 48 kHz 0.0001 4.50 4.75 5.00 5.25 122 4.50 5.50 VCC − Supply Voltage − V 4.75 5.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 132 130 Dynamic Range − dB THD+N − Total Harmonic Distortion + Noise − % 0.01 fS = 192 kHz 0.001 fS = 96 kHz 128 fS = 96 kHz fS = 48 kHz 126 124 fS = 48 kHz 0.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 −20 −20 −40 −60 Amplitude − dB Amplitude − dB −40 −80 −100 −120 −60 −80 −100 −120 −140 −140 −160 −180 −160 0 2 4 6 8 10 12 14 16 18 0 20 10 20 30 f − Frequency − kHz 40 50 60 70 80 90 100 f − Frequency − kHz Figure 19. −60-dB Output Spectrum, BW = 20 kHz Figure 20.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY 0 −20 Amplitude − dB −40 −60 −80 −100 −120 −140 −160 0 2 4 6 8 10 12 14 16 18 20 f − Frequency − kHz Figure 22. −60-dB Output Spectrum, DSD Mode NOTE: DSD mode (FIR-4), 32,768 point 8 average, TA = 25°C, VDD = 3.3 V, VCC = 5 V, measurement circuit is Figure 38.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM1792A requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1792A has a system clock detection circuit that automatically senses if the system clock is operating between 128 fS and 768 fS.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 VDD 2.4 V (Max) 2 V (Typ) 1.6 V (Min) Reset Reset Removal Internal Reset 1024 System Clocks System Clock Figure 25. Power-On Reset Timing RST (Pin 14) 50 % of VDD t(RST) Reset Reset Removal Internal Reset 1024 System Clocks System Clock t(RST) PARAMETERS MIN Reset pulse duration, LOW 20 Figure 26.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 AUDIO DATA INTERFACE Audio Serial Interface The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1792A on the rising edge of BCK. LRCK is the serial audio left/right word clock.
www.ti.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 External Digital Filter Interface and Timing The PCM1792A supports an external digital filter interface comprising a 3- or 4-wire synchronous serial port, which allows the use of an external digital filter. External filters include the Texas Instruments’ DF1704 and DF1706, the Pacific Microsonics PMD200, or a programmable digital signal processor.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 FUNCTION DESCRIPTIONS Zero Detect The PCM1792A has a zero-detect function. When the PCM1792A detects the zero conditions as shown in Table 2, the PCM1792A sets ZEROL (pin 1) and ZEROR (pin 2) to HIGH. Table 2. Zero Conditions MODE DETECTING CONDITION AND TIME PCM DATA is continuously LOW for 1024 LRCKs. External DF Mode DATA is continuously LOW for 1024 WDCKs.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 LSB MSB R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 Register Index (or Address) D4 D3 D2 D1 D0 Register Data Figure 29. Control Data Word Format for MDI MS MC MDI R/W A6 A5 A4 A3 A2 A1 A0 High Impedance MDO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 When Read Mode is Instructed NOTE: Bit 15 is used for selection of write or read.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 I2C Interface The PCM1792A supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave device. This protocol is explained in I2C specification 2.0. In I2C mode, the control terminals are changed as follows.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Write Register A master can write to any PCM1792A registers using single or multiple accesses. The master sends a PCM1792A slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by 1 automatically.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Case 2: 1. t(SCK) > 120 ns 2. t(S−HD) or t(RS−HD) < t(SCK) × 5 3. Spike noise exists on both SCL and SDA during the hold time. SCL Noise SDA When these conditions occur at the same time, the PCM1792A fails to detect a start condition. Case 3: 1. t(SCK) < 50 ns 2. t(SP) > t(SCK) 3. Spike noise exists on SCL just after SCL goes LOW. 4. Spike noise exists on SDA just before SCL goes LOW.
www.ti.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM1792A includes a number of user-programmable functions which are accessed via mode control registers. The registers are programmed using the serial control interface, which was previously discussed in this data sheet. Table 3 lists the available mode-control functions, along with their default reset conditions and associated register index. Table 3.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Register Map The mode control register map is shown in Table 4. Registers 16–21 include an R/W bit, which determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only. Table 4.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Register 18 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 R/W 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 B3 B2 DMF1 DMF0 B1 B0 DME MUTE R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATLD: Attenuation Load Control This bit is available for read and write.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 DME: Digital De-Emphasis Control This bit is available for read and write. Default value: 0 DME = 0 De-emphasis disabled (default) DME = 1 De-emphasis enabled The DME bit is used to enable or disable the de-emphasis function for both channels. MUTE: Soft Mute Control This bit is available for read and write.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 OPE: DAC Operation Control This bit is available for read and write. Default value: 0 OPE = 0 DAC operation enabled (default) OPE = 1 DAC operation disabled The OPE bit is used to enable or disable the analog output for both channels. Disabling the analog outputs forces them to the bipolar zero level (BPZ) even if digital audio data is present on the input. DFMS: Stereo DF Bypass Mode Select This bit is available for read and write.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 SRST: System Reset Control This bit is available for write only. Default value: 0 SRST = 0 Normal operation (default) SRST = 1 System reset operation (generate one reset pulse) The SRST bit is used to reset the PCM1792A to the initial system condition. DSD: DSD Interface Mode Control This bit is available for read and write.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 OS[1:0]: Delta-Sigma Oversampling Rate Selection These bits are available for read and write. Default value: 00 OS[1:0] Operation Speed Select 00 64 times fS (default) 01 32 times fS 10 128 times fS 11 Reserved The OS bits are used to change the oversampling rate of delta-sigma modulation. Use of this function enables the designer to stabilize the conditions at the post low-pass filter for different sampling rates.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 ZFGx: Zero-Detection Flag Where x = L or R, corresponding to the DAC output channel. These bits are available only for readback. Default value: 00 ZFGx = 0 Not zero ZFGx = 1 Zero detected These bits show zero conditions. Their status is the same as that of the zero flags at ZEROL (pin 1) and ZEROR (pin 2). See Zero Detect in the FUNCTION DESCRIPTIONS section.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 APPLICATION INFORMATION APPLICATION CIRCUIT The design of the application circuit is important in order to actually realize the high S/N ratio of which the PCM1792A is capable. This is because noise and distortion that are generated in an application circuit are not negligible. In the circuit of Figure 36, the output level is 2 V rms and 127 dB S/N is achieved. The circuit of Figure 37 can realize the highest performance.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 C1 2200 pF R1 750 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 270 Ω 6 + C3 2700 pF R3 560 Ω C19 33 pF 7 2 U1 NE5534 4 C15 0.1 µF 3 5 – 6 + 4 C12 0.1 µF VEE R4 560 Ω R6 270 Ω R7 100 Ω U3 LT1028 C16 0.1 µF C4 2700 pF VEE C2 2200 pF R2 750 Ω VCC C13 0.1 µF C18 22 pF 7 IOUT+ 2 3 5 – 8 6 + 4 U2 NE5534 C14 0.1 µF VCC = 15 V VEE = –15 V fc = 217 kHz VEE Figure 36.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 C1 2200 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 360 Ω 6 + C3 2700 pF R3 360 Ω C19 33 pF 7 2 U1 NE5534 4 C15 0.1 µF 3 5 – 6 + 4 C12 0.1 µF VEE R4 360 Ω R6 360 Ω R7 100 Ω U3 LT1028 C16 0.1 µF C4 2700 pF VEE C2 2200 pF R2 820 Ω VCC C13 0.1 µF C18 22 pF 7 IOUT+ 2 3 5 – 8 6 + 4 U2 NE5534 C14 0.1 µF VEE Figure 37. Measurement Circuit for PCM, VOUT = 4.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 C1 2200 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 330 Ω 6 + R3 110 Ω R10 68 Ω C3 18000 pF U1 NE5534 4 R8 220 Ω C5 10000 pF C4 47000 pF C15 0.1 µF C19 33 pF 7 2 3 5 – 6 + 4 C12 0.1 µF VEE R4 110 Ω R9 220 Ω R6 330 Ω R11 68 Ω R7 100 Ω U3 LT1028 C14 0.1 µF C6 10000 pF VEE C2 2200 pF R2 820 Ω VCC C13 0.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 IOUTL– (Pin 26) IOUT– IOUTL+ (Pin 25) IOUT+ OUT+ Figure 37 Circuit 3 1 2 IOUTR– (Pin 18) IOUT– OUT– Figure 37 Circuit IOUTR+ (Pin 17) Balanced Out IOUT+ Figure 39.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Application for Interfacing With an External Digital Filter For some applications, it may be desirable to use an external digital filter to perform the interpolation function, as it can provide improved stop-band attenuation when compared to the internal digital filter of the PCM1792A.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 WDCK (LRCK) 50% of VDD t(BCH) t(BCL) t(LB) 50% of VDD BCK t(BCY) t(BL) 50% of VDD DATA t(DS) t(DH) PARAMETER MIN t(BCY) BCK pulse cycle time t(BCL) BCK pulse duration, LOW MAX UNITS 20 ns 7 ns t(BCH) BCK pulse duration, HIGH t(BL) BCK rising edge to WDCK falling edge 7 ns 5 ns t(LB) t(DS) WDCK falling edge to BCK rising edge 5 ns DATA setup time 5 ns t(DH) DATA hold time 5 ns Figure 42.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 OS[1:0]: Delta-Sigma Modulator Oversampling Rate Selection Default value: 00 OS[1:0] Operation Speed Select 00 8 times WDCK (default) 01 4 times WDCK 10 16 times WDCK 11 Reserved The effective oversampling rate is determined by the oversampling performed by both the external digital filter and the delta-sigma modulator.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Pin Assignment When Using DSD Format Interface Several pins are redefined for DSD mode operation. These include: D D D D DATA (pin 5): DSDL as L-channel DSD data input LRCK (pin 4): DSDR as R-channel DSD data input SCK (pin 7): DBCK as bit-clock input BCK (pin 6): Set LOW (N/A) t = 1/(64 × 44.1 kHz) DBCK DSDL DSDR D0 D1 D2 D3 D4 Figure 44.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 ANALOG FIR FILTER PERFORMANCE IN DSD MODE GAIN vs FREQUENCY GAIN vs FREQUENCY 0 0 −1 −10 −2 −20 Gain – dB Gain – dB fc = 185 kHz Gain(1) = –6.6 dB −3 −30 −4 −40 −5 −50 −6 −60 0 50 100 150 200 0 500 f – Frequency – kHz 1000 1500 f – Frequency – kHz Figure 46. DSD Filter-1, Low BW Figure 47.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 GAIN vs FREQUENCY GAIN vs FREQUENCY 0 0 −1 −10 −2 −20 Gain – dB Gain – dB fc = 85 kHz Gain(1) = –1.5 dB −3 −30 −4 −40 −5 −50 −6 −60 0 50 100 150 200 0 f – Frequency – kHz 500 1000 1500 f – Frequency – kHz Figure 50. DSD Filter-3, Low BW Figure 51. DSD Filter-3, High BW GAIN vs FREQUENCY GAIN vs FREQUENCY 0 0 −1 −10 −2 −20 Gain – dB Gain – dB fc = 94 kHz Gain(1) = –3.
www.ti.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 TDMCA Mode Determination The PCM1792A recognizes the TDMCA mode automatically when it receives an LRCK signal with a pulse duration of two BCK clocks. If the TDMCA mode operation is not needed, the duty cycle of LRCK must be 50%. Figure 54 shows the LRCK and BCK timing that determines the TDMCA mode. The PCM1792A enters the TDMCA mode after two continuous TDMCA frames.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 DCO DCI NO Device ••• DCO DCOo DCIo DCO NO Device OUT DCOo DCIo OUT NO Device DCI ••• DCO IN/OUT Device ••• NO Device DCI IN/OUT Device DCI DCOi DCIi DCOi DCIi IN OUT Device ••• DCO DCO IN IN Device OUT Device DCI DCO DCI ••• IN Device DCI DCO DCI IN Chain OUT Chain Figure 55.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 DCII LRCK BCK IN/OUT DCOI Device (DIX1700) DI DCIO DO DCOO Device ID = 1 LRCK BCK IN Device (PCM1792A) DI DO LRCK DCI DCO Device ID = 2 NO Device DCI BCK DI DO DCO Device ID = 3 • • • FSX FSR CLKX CLKR DX DR LRCK OUT Device DCI BCK DI DO DCO Device ID = 2 TI DSP LRCK OUT Device DCI BCK DI DO DCO Device ID = 3 • • • Figure 56.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 LRCK BCK DID DI Device ID = 1 DCO1 Device ID = 2 DCO1 DCI2 Command Field Device ID = 3 DCO2 DCI3 • • • • • • Device ID = 30 DCO29 DCI30 58 BCK Figure 57. Device ID Determination Sequence TDMCA Frame In general, the TDMCA frame consists of the command field, extended command (EMD) field, and audio data fields. All of them are 32 bits in length, but the lowest byte has no meaning. The MSB is transferred first for each field.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 1/fS (256 PBCK Clocks) 7 Packets × 32 Bits LRCK BCK DI Ch1 CMD Ch2 Ch3 Ch4 Ch5 Ch6 Don’t Care CMD IN and OUT Channel Orders are Completely Independent DO Ch1 CMD Ch2 Figure 59. TDMCA Frame Example of 6-Ch DAC and 2-Ch ADC With Command Read Command Field The normal command field is defined as follows.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Audio Fields The audio field is 32 bits in length and the audio data is transferred MSB first, so the other fields must be stuffed with 0s as shown in the following example. audio data 31 16 MSB 24 bits 12 8 7 LSB 4 3 0 All 0s TDMCA Register Requirements TDMCA mode requires device ID and audio channel information, previously described.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 1/fS (384 PBCK Clocks) 9 Packets y 32 Bits LRCK BCK IN Daisy Chain CMD DI Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Ch8 Don’t Care DCI1 DID = 1 DID = 2 DID = 3 DID = 4 DCO1 DCI2 DCO2 DCI3 DCO3 DCI4 DCO4 Figure 61.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Command Packet LRCK BCK DI DID EMD DCO1 DCO2 • • • Figure 63.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 LRCK t(LB) t(BL) BCK t(BCY) t(DS) t(DH) DI t(DOE) DO t(DS) t(DH) DCI t(COE) DCO PARAMETER t(BCY) BCK pulse cycle time t(LB) LRCK setup time MIN MAX UNITS 20 ns 0 ns t(BL) t(DS) LRCK hold time 3 ns DI setup time 0 ns t(DH) t(DS) DI hold time 3 ns DCI setup time 0 ns 3 ns t(DH) DCI hold time t(DOE) DO output delay(1) t(COE) DCO output delay(1) (1) Load capacitance is 10 pF. Figure 64.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 THEORY OF OPERATION Upper 6 Bits ICOB Decoder 0–62 Level 0–66 Advanced DWA Digital Input 24 Bits 8 fS MSB and Lower 18 Bits 3rd-Order 5-Level Sigma-Delta Current Segment DAC Analog Output 0–4 Level Figure 65. Advanced Segments DAC The PCM1792A uses TI’s advanced segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The PCM1792A provides balanced current outputs.
www.ti.com SLES105B − FEBRUARY 2004 − REVISED NOVEMBER 2006 Analog output The following table and Figure 66 show the relationship between the digital input code and analog output. IOUTN [mA] IOUTP [mA] VOUTN [V] VOUTP [V] 800000 (–FS) 000000 (BPZ) 7FFFFF (+FS) –2.3 –6.2 –10.1 –10.1 –6.2 –2.3 –1.725 –4.650 –7.575 –7.575 –4.650 –1.725 VOUT [V] –2.821 0 2.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1792ADBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.2 10.5 2.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 15-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1792ADBR SSOP DB 28 2000 346.0 346.0 33.
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.