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

SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006

    

   

FEATURES

D 24-Bit Resolution

D Analog Performance:

− Dynamic Range: 132 dB (9 V RMS, Mono)

129 dB (4.5 V RMS, Stereo)

127 dB (2 V RMS, Stereo)

− THD+N: 0.0004%

D Differential Current Output: 7.8 mA p-p

D 8× Oversampling Digital Filter:

− Stop-Band Attenuation: –130 dB

− Pass-Band Ripple: ±0.00001 dB

D Sampling Frequency: 10 kHz to 200 kHz

D System Clock: 128, 192, 256, 384, 512, or

768 f

With Autodetect

D Accepts 16- and 24-Bit Audio Data

D PCM Data Formats: Standard, I

S, and

Left-Justified

D Optional Interface Available to External

Digital Filter or DSP

D Digital De-Emphasis

D Digital Filter Rolloff: Sharp or Slow

D Soft Mute

D Zero Flag

D Dual-Supply Operation:

− 5-V Analog, 3.3-V Digital

D 5-V Tolerant Digital Inputs

D Small 28-Lead SSOP Package

APPLICATIONS

D A/V Receivers

D DVD Players

D Musical Instruments

D HDTV Receivers

D Car Audio Systems

D Digital Multitrack Recorders

D Other Applications Requiring 24-Bit Audio

DESCRIPTION

The PCM1794A is a monolithic CMOS integrated circuit

that includes stereo digital-to-analog converters and

support circuitry in a small 28-lead SSOP package. The

data converters use TI’s advanced segment DAC

architecture to achieve excellent dynamic performance

and improved tolerance to clock jitter. The PCM1794A

provides balanced current outputs, allowing the user to

optimize analog performance externally. Sampling rates

up to 200 kHz are supported.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate

precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to

damage because very small parametric changes could cause the device not to meet its published specifications.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Summary of content (30 pages)

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! " #$% & ' ()*% !%$ '(!$% SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 FEATURES D 24-Bit Resolution D Analog Performance: − Dynamic Range: 132 dB (9 V RMS, Mono) 129 dB (4.5 V RMS, Stereo) 127 dB (2 V RMS, Stereo) − THD+N: 0.0004% D Differential Current Output: 7.8 mA p-p D 8× Oversampling Digital Filter: − Stop-Band Attenuation: –130 dB − Pass-Band Ripple: ±0.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 ORDERING INFORMATION PRODUCT PACKAGE PACKAGE CODE OPERATION TEMPERATURE RANGE PACKAGE MARKING PCM1794ADB 28-lead SSOP 28DB –25°C to 85°C PCM1794A ORDERING NUMBER TRANSPORT MEDIA PCM1794ADB Tube PCM1794ADBR Tape and reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) PCM1794A VCC1, VCC2L, VCC2R VDD Supply voltage –0.3 V to 6.5 V –0.3 V to 4 V ±0.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1794ADB PARAMETER TEST CONDITIONS MIN TYP MAX 0.0004% 0.0008% UNIT DYNAMIC PERFORMANCE (2-V RMS OUTPUT) (1)(2) THD+N at VOUT = 0 dB fS = 44.1 kHz fS = 96 kHz fS = 192 kHz EIAJ, A-weighted, fS = 44.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 ELECTRICAL CHARACTERISTICS (Continued) all specifications at TA = 25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 44.1 kHz, system clock = 256 fS, and 24-bit data, unless otherwise noted PCM1794ADB PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT Gain error –6 ±2 6 % of FSR Gain mismatch, channel-to-channel –3 ±0.5 3 % of FSR –2 ±0.5 2 % of FSR Bipolar zero error At BPZ Output current Full scale (0 dB) 7.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 TYPICAL PERFORMANCE CURVES DIGITAL FILTER Digital Filter Response AMPLITUDE vs FREQUENCY 0 2 0.00002 −50 1 0.00001 −100 Amplitude – dB Amplitude – dB AMPLITUDE vs FREQUENCY −150 −1 –0.00001 −200 0 1 2 3 4 0 −2 –0.00002 0.0 0.1 Frequency [× fS] 0.2 0.3 0.4 0.5 Frequency [× fS] Figure 1. Frequency Response, Sharp Rolloff Figure 2.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 De-Emphasis Filter DE-EMPHASIS LEVEL vs FREQUENCY DE-EMPHASIS ERROR vs FREQUENCY 0 20 0.020 fS = 44.1 kHz fS = 44.1 kHz 15 0.015 De-Emphasis Error – dB De-Emphasis Level – dB −2 −4 −6 10 0.010 5 0.005 0 −5 –0.005 −10 –0.010 −8 −15 –0.015 −10 −20 –0.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics TOTAL HARMONIC DISTORTION + NOISE vs SUPPLY VOLTAGE DYNAMIC RANGE vs SUPPLY VOLTAGE 132 130 fS = 96 kHz Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 0.01 fS = 192 kHz 0.001 fS = 96 kHz fS = 48 kHz 128 fS = 192 kHz 126 124 fS = 48 kHz 0.0001 4.50 4.75 5.00 5.25 122 4.50 5.50 VCC – Supply Voltage – V 4.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 Temperature Characteristics TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE vs FREE-AIR TEMPERATURE 132 130 Dynamic Range – dB THD+N – Total Harmonic Distortion + Noise – % 0.01 fS = 192 kHz 0.001 fS = 96 kHz 128 fS = 96 kHz fS = 48 kHz 126 124 fS = 48 kHz 0.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 0 −20 −20 −40 −60 Amplitude – dB Amplitude – dB −40 −80 −100 −120 −60 −80 −100 −120 −140 −140 −160 −180 −160 0 2 4 6 8 10 12 14 16 18 20 0 10 20 f – Frequency – kHz 30 40 50 60 70 80 90 100 f – Frequency – kHz NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.3 V, NOTE: fS = 48 kHz, 32768 point 8 average, TA = 25°C, VDD = 3.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM1794A requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1794A has a system clock detection circuit that automatically senses the frequency at which the system clock is operating. Table 1 shows examples of system clock frequencies for common audio sampling rates.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 VDD 2.4 V (Max) 2 V (Typ) 1.6 V (Min) Reset Reset Removal Internal Reset 1024 System Clocks System Clock Figure 19. Power-On Reset Timing RST (Pin 14) 50 % of VDD t(RST) Reset Reset Removal Internal Reset 1024 System Clocks System Clock t(RST) PARAMETERS MIN Reset pulse duration, LOW 20 Figure 20.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 AUDIO DATA INTERFACE Audio Serial Interface The audio interface port is a 3-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is the serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio interface. Serial data is clocked into the PCM1794A on the rising edge of BCK. LRCK is the serial audio left/right word clock.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 FUNCTION DESCRIPTIONS Audio data format Audio format is selected using FMT0 (pin 11) and FMT1 (pin 12). The PCM1794A also supports monaural mode and DF bypass mode using MONO (pin 1) and CHSL (pin 2). The PCM1794A can select the DF rolloff characteristics. Table 2.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 TYPICAL CONNECTION DIAGRAM Cf 5V Rf 0.1 µF Controller PCM Audio Data Source 0.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 APPLICATION INFORMATION APPLICATION CIRCUIT The design of the application circuit is very important in order to actually realize the high S/N ratio of which the PCM1794A is capable. This is because noise and distortion that are generated in an application circuit are not negligible. In the circuit of Figure 24, the output level is 2 V RMS, and 127 dB S/N is achieved. The circuit of Figure 25 can realize the highest performance.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 C1 2200 pF R1 750 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 270 Ω 6 + C3 2700 pF R3 560 Ω C19 33 pF 7 2 U1 NE5534 4 C15 0.1 µF 3 5 – 6 + 4 C12 0.1 µF VEE R4 560 Ω R6 270 Ω U3 LT1028 C16 0.1 µF C4 2700 pF VEE C2 2200 pF R2 750 Ω VCC C13 0.1 µF C18 22 pF 7 IOUT+ 2 3 5 – VCC = 15 V VEE = –15 V fC = 217 kHz 8 6 + 4 U2 NE5534 C14 0.1 µF VEE Figure 24.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 C1 2200 pF R1 820 Ω VCC VCC C11 0.1 µF C17 22 pF 7 IOUT– 5 2 8 – 3 R5 360 Ω 6 + C3 2700 pF R3 360 Ω C19 33 pF 7 2 U1 NE5534 4 C15 0.1 µF 3 5 – 6 + 4 C12 0.1 µF VEE R4 360 Ω R6 360 Ω R7 100 Ω U3 LT1028 C16 0.1 µF C4 2700 pF VEE C2 2200 pF R2 820 Ω VCC C13 0.1 µF C18 22 pF 7 IOUT+ 2 3 VCC = 15 V VEE = –15 V fC = 162 kHz 5 – 8 6 + 4 U2 NE5534 C14 0.1 µF VEE Figure 25. Measurement Circuit, VOUT = 4.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 IOUTL– (Pin 26) IOUT– OUT+ Figure 25 Circuit IOUTL+ (Pin 25) IOUT+ 3 1 2 IOUTR– (Pin 18) IOUT– OUT– Figure 25 Circuit IOUTR+ (Pin 17) Balanced Out IOUT+ Figure 26.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 Application for Interfacing With an External Digital Filter For some applications, it may be desirable to use a programmable digital signal processor as an external digital filter to perform the interpolation function. The following pin settings enable the external digital filter application mode.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 WDCK 50% of VDD t(BCH) t(BCL) t(LB) 50% of VDD BCK t(BCY) t(BL) 50% of VDD DATA t(DS) t(DH) PARAMETER MIN t(BCY) BCK pulse cycle time t(BCL) BCK pulse duration, LOW MAX UNITS 20 ns 7 ns t(BCH) BCK pulse duration, HIGH t(BL) BCK rising edge to WDCK falling edge 7 ns 5 ns t(LB) t(DS) WDCK falling edge to BCK rising edge 5 ns DATA setup time 5 ns t(DH) DATA hold time 5 ns Figure 29.
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www.ti.com SLES117A – AUGUST 2004 – REVISED NOVEMBER 2006 Analog output The following table and Figure 31 show the relationship between the digital input code and analog output. IOUTN [mA] IOUTP [mA] VOUTN [V] VOUTP [V] 800000 (–FS) 000000 (BPZ) 7FFFFF (+FS) –2.3 –6.2 –10.1 –10.1 –6.2 –2.3 –1.725 –4.65 –7.575 –7.575 –4.65 –1.725 VOUT [V] –2.821 0 2.821 NOTE: VOUTN is the output of U1, VOUTP is the output of U2, and VOUT is the output of U3 in the measurement circuit of Figure 24.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1794ADBR Package Package Pins Type Drawing SSOP DB 28 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.5 10.8 2.4 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1794ADBR SSOP DB 28 2000 336.6 336.6 28.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.