Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) SSOP 28

FEATURES APPLICATIONS

DESCRIPTION

PCM1795

www.ti.com

........................................................................................................................................................................................................ SLES248 – MAY 2009

32-Bit, 192-kHz Sampling, Advanced Segment,

Stereo Audio Digital-to-Analog Converter

• A/V Receivers

234567

• 32-Bit Resolution

• SACD Players

• Analog Performance:

• DVD Players

– Dynamic Range: 123 dB

• HDTV Receivers

– THD+N: 0.0005%

• Car Audio Systems

• Differential Current Output: 3.9 mA

• Digital Multitrack Recorders

• 8 × Oversampling Digital Filter:

• Other Applications Requiring 32-Bit Audio

– Stop Band Attenuation: – 98 dB

– Passband Ripple: ± 0.0002 dB

• Sampling Frequency: 10 kHz to 200 kHz

The PCM1795 is a monolithic CMOS integrated

• System Clock: 128, 192, 256, 384, 512, or

circuit that includes stereo digital-to-analog

768 f

With Autodetect

converters (DACs) and support circuitry in a small

SSOP-28 package. The data converters use TI ’ s

• Accepts 16-, 24-, and 32-Bit Audio Data

advanced segment DAC architecture to achieve

• PCM Data Formats: Standard, I

S™, and

excellent dynamic performance and improved

Left-Justified

tolerance to clock jitter. The PCM1795 provides

• DSD Format Interface Available

balanced current outputs, allowing the user to

optimize analog performance externally. The

• Interface Available for Optional External Digital

PCM1795 accepts pulse code modulation (PCM) and

Filter or DSP

direct stream digital (DSD) audio data formats,

• TDMCA or Serial Port ( SPI™/ I

C™)

providing an easy interface to audio digital signal

• User-Programmable Mode Controls:

processors (DSPs) and decoder chips. The PCM1795

also interfaces with external digital filter devices such

– Digital Attenuation: 0 dB to – 120 dB,

as the DF1704 , DF1706 , and the PMD200 from

0.5-dB/Step

Pacific Microsonics™. Sampling rates up to 200 kHz

– Digital De-Emphasis

are supported. A full set of user-programmable

– Digital Filter Roll-Off: Sharp or Slow

functions is accessible through an SPI or I

C serial

control port that supports register write and readback

– Soft Mute

functions. The PCM1795 also supports the

– Zero Flag for Each Output

time-division-multiplexed (TDM) command and audio

• Compatible With PCM1792A and PCM1796

(TDMCA) data format.

(Pins and Mode Controls)

• Dual Supply Operation:

– 5-V Analog, 3.3-V Digital

• 5-V Tolerant Digital Inputs

• Small SSOP-28 Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 System Two, Audio Precision are trademarks of Audio Precision, Inc.

3 SPI is a trademark of Motorola.

4 I2S, I2C are trademarks of NXP Semiconductors.

5 Pacific Microsonics is a trademark of Pacific Microsonics, Inc.

6 Super Audio CD is a trademark of Sony Corporation.

7 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (56 pages)

PAGE 1
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 32-Bit, 192-kHz Sampling, Advanced Segment, Stereo Audio Digital-to-Analog Converter FEATURES APPLICATIONS • 32-Bit Resolution • Analog Performance: – Dynamic Range: 123 dB – THD+N: 0.0005% • Differential Current Output: 3.
PAGE 2
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
PAGE 3
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 ELECTRICAL CHARACTERISTICS All specifications at TA = +25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 32-bit data, unless otherwise noted.
PAGE 4
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 32-bit data, unless otherwise noted.
PAGE 5
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VCC1 = VCC2L = VCC2R = 5 V, VDD = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 32-bit data, unless otherwise noted. PCM1795 DB PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 3.3 3.6 VDC 4.
PAGE 6
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.
PAGE 7
PCM1795 www.ti.com ........................................................................................................................................................................................................
PAGE 8
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Table 1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO.
PAGE 9
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 TIMING CHARACTERISTICS Repeated Start Start Stop t(SDA-F) t(D-HD) t(BUF) t(D-SU) t(SDA-R) t(P-SU) SDA t(SCL-R) t(RS-HD) t(SP) t(LOW) SCL t(SCL-F) t(HI) t(RS-SU) t(S-HD) Figure 1.
PAGE 10
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: DIGITAL FILTER Digital Filter Response AMPLITUDE vs FREQUENCY 0 AMPLITUDE vs FREQUENCY 0.0005 Frequency Response Sharp Roll-Off -20 0.0003 Amplitude (dB) -40 Amplitude (dB) Passband Ripple Sharp Roll-Off 0.0004 -60 -80 -100 0.0002 0.
PAGE 11
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 TYPICAL CHARACTERISTICS: DIGITAL FILTER De-Emphasis Filter DE-EMPHASIS LEVEL vs FREQUENCY 0 fS = 32 kHz -1 fS = 32 kHz 0.4 -2 De-Emphasis Error (dB) De-Emphasis Level (dB) DE-EMPHASIS ERROR vs FREQUENCY 0.5 -3 -4 -5 -6 -7 -8 -9 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.
PAGE 12
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE Supply Voltage Characteristics PCM mode, TA = +25°C, and VDD = 3.3 V; measured with circuit shown in Figure 52, unless otherwise noted.
PAGE 13
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE Temperature Characteristics PCM mode, VDD = 3.3 V, and VCC = 5 V; measured with circuit shown in Figure 52, unless otherwise noted.
PAGE 14
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: ANALOG DYNAMIC PERFORMANCE (continued) PCM mode, VDD = 3.3 V, and VCC = 5 V; measured with circuit shown in Figure 52, unless otherwise noted.
PAGE 15
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 TYPICAL CHARACTERISTICS: ANALOG FIR FILTER PERFORMANCE IN DSD MODE All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.
PAGE 16
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS: ANALOG FIR FILTER PERFORMANCE IN DSD MODE (continued) All specifications at DBCK = 2.8224 MHz (44.1 kHz × 64 fS), and 50% modulation DSD data input, unless otherwise noted.
PAGE 17
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 GENERAL DESCRIPTION SYSTEM CLOCK AND RESET FUNCTIONS System Clock Input The PCM1795 requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 7).
PAGE 18
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Power-On and External Reset Functions The PCM1795 includes a power-on reset function, as shown in Figure 35. With VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time VDD > 2 V.
PAGE 19
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 AUDIO DATA INTERFACE Audio Serial Interface The audio interface port is a three-wire serial port. It includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5).
PAGE 20
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.
PAGE 21
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 External Digital Filter Interface and Timing The PCM1795 supports an external digital filter interface that consists of a three- or four-wire synchronous serial port that allows the use of an external digital filter.
PAGE 22
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Register Read/Write Operation All read/write operations for the serial control port use 16-bit data words. Figure 41 shows the control data word format. The most significant bit (MSB) is the read/write (R/W) bit. For write operations, the R/W bit must be set to '0'.
PAGE 23
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 t(MHH) 1.4 V MS t(MSS) t(MCH) t(MCL) t(MSH) MC 1.4 V t(MCY) LSB MDI t(MDS) 1.4 V t(MOS) t(MDH) 50% of VDD MDO Figure 43.
PAGE 24
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Slave Address The PCM1795 has seven bits for its own slave address, as shown in Figure 44. The first five bits (MSBs) of the slave address are factory preset to 10011.
PAGE 25
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 Write Register A master can write to any PCM1795 registers using single or multiple accesses. The master sends a PCM1795 slave address with a write bit, a register address, and the data.
PAGE 26
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Case 2: 1. t(SCK) > 120 ns 2. t(S–HD) or t(RS–HD) < t(SCK) × 5 3. Spike noise exists on both SCL and SDA during the hold time. SCL Noise SDA Figure 49. Case 2 When these conditions occur at the same time, the PCM1795 fails to detect a start condition. Case 3: 1.
PAGE 27
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 MODE CONTROL REGISTERS User-Programmable Mode Controls The PCM1795 includes a number of user-programmable functions that are accessed via mode control registers.
PAGE 28
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Table 8.
PAGE 29
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 Table 10. Attenuation Levels Register 18 ATx[7:0] DECIMAL VALUE ATTENUATION LEVEL SETTING 1111 1111b 255 0 dB, no attenuation (default) 1111 1110b 254 –0.5 dB 1111 1101b 253 –1.0 dB — — — 0001 0000b 16 –119.5 dB 0000 1111b 15 –120.
PAGE 30
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com The FMT[2:0] bits are used to select the data format for the serial audio interface. For the external digital filter interface mode (DFTH mode), this register is operated as shown in the Application for External Digital Filter Interface section.
PAGE 31
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 REV: Output Phase Reversal This bit is available for read and write. Default value: 0 REV Output Setting REV = 0 Normal output (default) REV = 1 Inverted output The REV bit is used to invert the output phase for both channels.
PAGE 32
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com FLT: Digital Filter Roll-Off Control This bit is available for read and write. Default value: 0 FLT Roll-Off Control FLT = 0 Sharp roll-off (default) FLT = 1 Slow roll-off The FLT bit is used to select the digital filter roll-off characteristic.
PAGE 33
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 DFTH: Digital Filter Bypass (or Through Mode) Control This bit is available for read and write.
PAGE 34
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Register 21 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 R/W 0 0 1 0 1 0 1 RSV RSV RSV RSV RSV DZ1 DZ0 PCMZ R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed.
PAGE 35
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 Register 23 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 R 0 0 1 0 1 1 1 RSV RSV RSV ID4 ID3 ID2 ID1 ID0 Read Mode Select Value is always '1', specifying the readback mode.
PAGE 36
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com APPLICATION CIRCUIT The design of the application circuit is very important in order to actually realize the high S/N ratio of which the PCM1795 is capable, because noise and distortion that are generated in an application circuit are not negligible.
PAGE 37
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 C1 2700 pF R1 820 W VCC VCC C11 0.1 mF 7 IOUT- 5 2 R5 200 W C17 22 pF R3 220 W 8 – 6 3 + 4 R7 180 W C5 27000 pF U1 NE5534 C12 0.1 mF C15 0.
PAGE 38
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com C1 2200 pF R1 820 W VCC VCC C11 0.1 mF 7 IOUT- 5 2 8 – 6 3 R5 150 W C17 22 pF + R3 91 W C3 22000 pF U1 NE5534 4 C12 0.1 mF VEE R8 75 W C15 0.
PAGE 39
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 IOUT- IOUTL- (Pin 26) Circuit OUT+ (1) IOUT+ IOUTL+ (Pin 25) 3 1 2 IOUT- IOUTR- (Pin 18) Circuit OUT- (1) Balanced Out IOUT+ IOUTR+ (Pin 17) (1) Circuit corresponds to Figure 52. Figure 54.
PAGE 40
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.
PAGE 41
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 System Clock (SCK) and Interface Timing The PCM1795 in an application using an external digital filter requires the synchronization of WDCK and the system clock. The system clock is phase-free with respect to WDCK.
PAGE 42
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com FUNCTIONS AVAILABLE IN THE EXTERNAL DIGITAL FILTER MODE The external digital filter mode is selected by setting DSD = 0 (register 20, B5) and DFTH = 1 (register 20, B4). The external digital filter mode allows access to the majority of the PCM1795 mode control functions.
PAGE 43
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 APPLICATION FOR DSD FORMAT (DSD MODE) INTERFACE Figure 58 shows a connection diagram for DSD mode. DSD Decoder PCM1796 1 ZEROL 2 ZEROR 3 MSEL DATA_R 4 LRCK DATA_L 5 DATA 6 BCK 7 SCK Bit Clock Figure 58.
PAGE 44
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Requirements for System Clock For operation in DSD mode, the bit clock (DBCK) is required on pin 7 of the PCM1795. The frequency of the bit clock can be N times the sampling frequency. Generally, N is 64 in DSD applications.
PAGE 45
PCM1795 www.ti.com ........................................................................................................................................................................................................
PAGE 46
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com TDMCA Terminals TDMCA requires six signals: four signals are for the command and audio data interface, and one pair for daisy-chaining. These signals can be shared as shown in Table 15.
PAGE 47
PCM1795 www.ti.com ........................................................................................................................................................................................................
PAGE 48
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com LRCK BCK DID DI Device ID = 1 DCO1 Device ID = 2 DCO1, DCI2 Device ID = 3 DCO2, DCI3 Command Field 58 BCKs Device ID = 30 DCO29, DCI30 Figure 64.
PAGE 49
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 1/fS (256 BCK Clocks) 7 Packets ´ 32 Bits LRCK BCK DI Ch 1 CMD Ch 2 Ch 3 Ch 4 Ch 5 Don’t Care Ch 6 CMD IN and OUT Channel Orders are Completely Independent DO Ch 1 CMD Ch 2 Figure 66.
PAGE 50
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Extended Command Field The extended command field is the same as the command field, except that it does not have a DID flag. Figure 68 defines the extended command field.
PAGE 51
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 TDMCA Mode Operation DCO specifies the owner of the next audio channel in TDMCA mode operation. When a device retrieves its own audio channel data, DCO goes high during the last audio channel period. Figure 71 shows the DCO output timing in TDMCA mode operation.
PAGE 52
PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Command Packet LRCK BCK DI DID EMD DCO1 DCO2 ¼ Figure 73. DCO Output Timing with Skip Operation (for Command Packet 1) LRCK t(LB) t(BL) BCK t(BCY) t(DS) t(DH) DI t(DOE) DO t(DS) t(DH) DCI t(COE) DCO Figure 74. AC Timing of Daisy-Chain Signals Table 16.
PAGE 53
PCM1795 www.ti.com ........................................................................................................................................................................................................ SLES248 – MAY 2009 ANALOG OUTPUT Table 17 and Figure 75 show the relationship between the digital input code and analog output. Table 17. Analog Output Current and Voltage (1) (1) PARAMETER 800000 (–FS) 000000 (BPZ) 7FFFFF (+FS) IOUTN (mA) –1.5 –3.5 –5.5 IOUTP (mA) –5.5 3.5 –1.
PAGE 54
PACKAGE OPTION ADDENDUM www.ti.
PAGE 55
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 56
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.