Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - ADC 24 Bit SSOP 20

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FEATURES APPLICATIONS

DESCRIPTION

PCM1802

SLES023C – DECEMBER 2001 – REVISED JANUARY 2005

SINGLE-ENDED ANALOG-INPUT

24-BIT, 96-kHz STEREO A/D CONVERTER

• AV Amplifier Receiver

• 24-Bit Delta-Sigma Stereo A/D Converter

• MD Player

• Single-Ended Voltage Input: 3 V p-p

• CD Recorder

• Antialiasing Filter Included

• Multitrack Receiver

• Oversampling Decimation Filter

• Electric Musical Instrument

– Oversampling Frequency: × 64, × 128

– Pass-Band Ripple: ± 0.05 dB

– Stop-Band Attenuation: –65 dB

The PCM1802 is a high-performance, low-cost,

– On-Chip High-Pass Filter (HPF): 0.84 Hz

single-chip stereo analog-to-digital converter with

(44.1 kHz)

single-ended analog voltage input. The PCM1802

uses a delta-sigma modulator with 64- or 128-times

• High Performance

oversampling, and includes a digital decimation filter

– THD+N: 96 dB (Typical)

and high-pass filter (HPF), which removes the dc

– SNR: 105 dB (Typical)

component of the input signal. For various appli-

– Dynamic Range: 105 dB (Typical)

cations, the PCM1802 supports master and slave

modes and four data formats in serial interface. The

• PCM Audio Interface

PCM1802 is suitable for a wide variety of cost-

– Master/Slave Mode Selectable

sensitive consumer applications where good perform-

– Data Formats: 24-Bit Left-Justified; 24-Bit

ance, 5-V analog supply, and 3.3-V digital supply

S; 20-, 24-Bit Right-Justified operation is required. The PCM1802 is fabricated

using a highly advanced CMOS process and is

• Sampling Rate: 16 kHz to 96 kHz

available in the DB 20-pin SSOP package.

• System Clock: 256 f

, 384 f

, 512 f

, 768 f

• Dual Power Supplies: 5 V for Analog, 3.3 V for

Digital

• Package: 20-Pin SSOP

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
PCM1802 SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 SINGLE-ENDED ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • • 24-Bit Delta-Sigma Stereo A/D Converter Single-Ended Voltage Input: 3 V p-p Antialiasing Filter Included Oversampling Decimation Filter – Oversampling Frequency: ×64, ×128 – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter (HPF): 0.84 Hz (44.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 Terminal Functions TERMINAL NAME PIN AGND 6 BCK 11 BYPAS 8 DGND DOUT I/O – DESCRIPTIONS Analog GND I/O Bit clock input/output (1) I HPF bypass control. Low: normal mode (dc cut); High: bypass mode (through) (2) 13 – Digital GND 12 O Audio data output FMT0 17 I Audio data format select 0. See data format (2) FMT1 18 I Audio data format select 1.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 ELECTRICAL CHARACTERISTICS (continued) all specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data (unless otherwise noted) PCM1802DB TEST CONDITIONS Channel separation MIN fS = 44.1 kHz fS = 96 kHz 96 (9) TYP MAX 103 UNIT dB 98 ANALOG INPUT Input voltage 0.6 VCC Vp-p Center voltage (VREF1) 0.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER Digital Filter—Decimation Filter Frequency Response AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 50 50 Oversampling Ratio = 128 Oversampling Ratio = 64 0 Amplitude − dB Amplitude − dB 0 −50 −100 −150 −50 −100 −150 −200 −200 0 8 16 24 32 40 48 56 64 Frequency [× fS] 0 8 16 24 32 Frequency [× fS] G001 Figure 1. Overall Characteristics G002 Figure 2.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) HPF (High-Pass Filter) Frequency Response AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0.2 0 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 −1.0 0.1 0.2 0.3 Frequency [× fS/1000] 0 0.4 1 2 3 4 Frequency [× fS/1000] G005 Figure 5. HPF Stop-Band Characteristics G006 Figure 6.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 TYPICAL PERFORMANCE CURVES TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE and SNR vs FREE-AIR TEMPERATURE 110 109 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise − % 0.004 0.003 0.002 107 Dynamic Range 106 105 SNR 104 103 102 101 0.001 −50 −25 0 25 50 75 TA − Free-Air Temperature − °C 100 −50 100 −25 0 25 50 75 TA − Free-Air Temperature − °C G009 Figure 9. Figure 10.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 TYPICAL PERFORMANCE CURVES (continued) TOTAL HARMONIC DISTORTION + NOISE vs fSAMPLE CONDITION DYNAMIC RANGE and SNR vs fSAMPLE CONDITION 110 †f S = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128. ‡f = 96 kHz, System Clock = 256 f , S S Oversampling Ratio = ×64. †f S = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128. ‡f = 96 kHz, System Clock = 256 f , S S Oversampling Ratio = ×64.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 TYPICAL PERFORMANCE CURVES (continued) TOTAL HARMONIC DISTORTION + NOISE vs SIGNAL LEVEL THD+N − Total Harmonic Distortion + Noise − % 100 10 1 0.1 0.01 0.001 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level − dB G017 Figure 17. Supply Current SUPPLY CURRENT vs fSAMPLE CONDITION ICC and IDD − Supply Current − mA 30 ICC 25 20 15 IDD 10 †f S = 48 kHz, System Clock = 256 fS, Oversampling Ratio = ×128.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 PRINCIPLES OF OPERATION The PCM1802 consists of a reference circuit, two channels of single-ended-to-differential converter, a fifth-order delta-sigma modulator with full differential architecture, a decimation filter with high-pass filter, and a serial interface circuit.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 PRINCIPLES OF OPERATION (continued) 1 µF 20 kΩ + VINL − 1 − + (+) + (−) VREF1 Delta-Sigma Modulator 3 + 0.1 µF Reference 10 µF VREF2 4 VCC 5 S0011-05 Figure 20.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 PRINCIPLES OF OPERATION (continued) System Clock The PCM1802 supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 15). The PCM1802 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, 512 fS, or 768 fS in slave mode.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 Power-On Reset Sequence The PCM1802 has an internal power-on reset circuit, and initialization (reset) is performed automatically when the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts after VDD > 2.2 V (typical), the PCM1802 stays in the reset state and the digital output is forced to zero.
PAGE 15
PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 Interface Mode The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1 (pin 20) and MODE0 (pin 19) as shown in Table 2. In master mode, the PCM1802 provides the timing for serial audio data communications between the PCM1802 and the digital audio processor or external circuit. In slave mode, the PCM1802 receives the timing for data transfer from an external controller. Table 2.
PAGE 16
PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 Interface Timing Figure 25 and Figure 27 illustrate the interface timing in slave mode and master mode, respectively.
PAGE 17
PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 1.4 V FSYNC t(FSSU) t(FSHD) t(LRCP) 1.4 V LRCK t(BCKL) t(BCKH) t(LRSU) t(LRHD) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.
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PCM1802 www.ti.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 t(FSYP) 0.5 VDD FSYNC t(CKFS) t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(BCKP) t(CKDO) t(LRDO) 0.
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PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 It is recommended to set PDWN low to get stable analog performance when the sampling rate, interface mode, data format, or oversampling control is changed. Synchronization Lost State of Synchronization SYNCHRONOUS Resynchronization ASYNCHRONOUS SYNCHRONOUS 1/fS DOUT NORMAL DATA 32/fS UNDEFINED DATA ZERO DATA NORMAL DATA T0020-05 Figure 28.
PAGE 21
PCM1802 www.ti.com SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 APPLICATION INFORMATION Typical Circuit Connection Diagram Figure 29 illustrates a typical circuit connection diagram in which the cutoff frequency of the input HPF is about 8 Hz.
PAGE 22
PCM1802 SLES023C – DECEMBER 2001 – REVISED JANUARY 2005 www.ti.com APPLICATION INFORMATION (continued) Board Design and Layout Considerations VCC, VDD Pins The digital and analog power supply lines to the PCM1802 should be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF tantalum capacitors as close to the pins as possible to maximize the dynamic performance of the ADC.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1802DBR Package Package Pins Type Drawing SSOP DB 20 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.5 7.6 2.4 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1802DBR SSOP DB 20 2000 336.6 336.6 28.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.