Datasheet

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FEATURES APPLICATIONS

DESCRIPTION

PCM1803A

SLES142A – JUNE 2005 – REVISED AUGUST 2006

SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER

• AV Amplifier Receiver

• 24-Bit Delta-Sigma Stereo A/D Converter

• MD Player

• Single-Ended Voltage Input: 3 Vp-p

• CD Recorder

• Oversampling Decimation Filter:

• Multitrack Receiver

– Oversampling Frequency: ×64, ×128

• Electric Musical Instrument

– Pass-Band Ripple: ±0.05 dB

– Stop-Band Attenuation: –65 dB

– On-Chip High-Pass Filter: 0.84 Hz (44.1 kHz)

The PCM1803A is high-performance, low-cost,

• High-Performance:

single-chip stereo analog-to-digital converter with

– THD+N: –95 dB (Typically)

single-ended analog voltage input. The PCM1803A

uses a delta-sigma modulator with 64- and 128-times

– SNR: 103 dB (Typically)

oversampling, and includes a digital decimation filter

– Dynamic Range: 103 dB (Typically)

and high-pass filter, which removes the dc

• PCM Audio Interface:

component of the input signal. For various

applications, the PCM1803A supports master and

– Master/Slave Mode Selectable

slave modes and four data formats in serial interface.

– Data Formats:

The PCM1803A is suitable for a wide variety of

• 24-Bit Left-Justified

cost-sensitive consumer applications where good

performance and operation from a 5-V analog supply

• 24-Bit I

and 3.3-V digital supply are required. The

• 20-, 24-Bit Right-Justified

PCM1803A is fabricated using a highly advanced

• Sampling Rate: 16 kHz to 96 kHz

CMOS process and is available in a small 20-pin

SSOP package.

• System Clock: 256 f

, 384 f

, 512 f

, 768 f

• Dual Power Supplies: 5 V for Analog, 3.3 V

for Digital

• Package: 20-Pin SSOP

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER FEATURES APPLICATIONS • • • • • • • • • • • • • • 24-Bit Delta-Sigma Stereo A/D Converter Single-Ended Voltage Input: 3 Vp-p Oversampling Decimation Filter: – Oversampling Frequency: ×64, ×128 – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.84 Hz (44.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME NO. I/O AGND 6 – BCK 11 I/O DESCRIPTION Analog GND Audio data bit clock input/output (1) BYPAS 8 I HPF bypass control. LOW: Normal mode (dc reject); HIGH: Bypass mode (through) (2) DGND 13 – Digital GND DOUT 12 O Audio data digital output FMT0 17 I Audio data format select input 0. See Data Format section. (2) FMT1 18 I Audio data format select input 1.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range MIN NOM MAX Analog supply voltage, VCC 4.5 5 5.5 V Digital supply voltage, VDD 2.7 3.3 3.6 V Analog input voltage, full-scale (–0 dB) 3 Digital input logic family Digital input clock frequency UNIT Vp-p TTL System clock Sampling clock 8.192 49.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VIN = –0.5 dB, fS = 44.1 kHz –95 –89 VIN = –0.5 dB, fS = 96 kHz (6) –93 VIN = –60 dB, fS = 44.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data (unless otherwise noted) LOW-CUT FILTER FREQUENCY RESPONSE HPF STOP-BAND CHARACTERISTICS HPF PASS-BAND CHARACTERISTICS 0.2 0 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 −1.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data (unless otherwise noted) −90 110 −91 109 −92 108 −93 −94 −95 −96 −97 −98 −99 −100 −50 107 106 105 103 SNR 102 −25 0 25 50 75 100 −50 100 0 25 50 75 100 G007 G008 Figure 7. Figure 8.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 44.1 kHz, system clock = 384 fS, oversampling ratio = ×128, 24-bit data (unless otherwise noted) THD+N − Total Harmonic Distortion + Noise − dB TOTAL HARMONIC DISTORTION + NOISE vs SIGNAL LEVEL 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level − dB G015 Figure 15.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 DEVICE INFORMATION SYSTEM CLOCK The PCM1803A supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 15). The PCM1803A has a system clock-detection circuit that automatically senses if the system clock is operating at 256 fS, 384 fS, 512 fS, or 768 fS in slave mode.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 2.6 V 2.2 V 1.8 V VDD Reset Reset Removal Internal Reset 1024 System Clocks 4480 / fS System Clock DOUT Zero Data Normal Data T0014-05 Figure 18. Internal Power-On-Reset Timing SERIAL AUDIO DATA INTERFACE The PCM1803A interfaces the audio system through BCK (pin 11), LRCK (pin 10), and DOUT (pin 12).
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 Table 3.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 INTERFACE TIMING Figure 20 illustrates the interface timing in slave mode; Figure 21 and Figure 22 illustrate the interface timing in master mode. t(LRCP) 1.4 V LRCK t(BCKL) t(LRSU) t(BCKH) t(LRHD) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0017-02 SYMBOL PARAMETER t(BCKP) BCK period t(BCKH) MIN TYP MAX UNIT 1/(64 fS) ns BCK pulse duration, HIGH 1.5 × t(SCKI) ns t(BCKL) BCK pulse duration, LOW 1.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(CKDO) t(BCKP) t(LRDO) 0.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1803A operates under LRCK, synchronized with system clock SCKI. The PCM1803A does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI.
PAGE 17
PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 POWER DOWN PDWN (pin 7) controls operation of the entire ADC. During power-down mode, supply current for the analog portion is shut down and the digital portion is reset; also, DOUT (pin 12) is disabled. It is acceptable to halt the system clock during power-down mode so that power dissipation is minimized. The minimum LOW pulse duration on the PDWN pin is 100 ns.
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PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 APPLICATION INFORMATION TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 24 illustrates a typical circuit connection diagram where the cutoff frequency of the input HPF is about 160 kHz.
PAGE 19
PCM1803A www.ti.com SLES142A – JUNE 2005 – REVISED AUGUST 2006 APPLICATION INFORMATION (continued) BOARD DESIGN and LAYOUT CONSIDERATIONS VCC, VDD Pins The digital and analog power-supply lines to the PCM1803A should be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF electrolytic capacitors, as close to the pins as possible, to maximize the dynamic performance of the ADC.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1803ADBR Package Package Pins Type Drawing SSOP DB 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 17.4 Pack Materials-Page 1 8.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.6 2.4 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Nov-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1803ADBR SSOP DB 20 2000 336.6 336.6 28.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.