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FEATURES APPLICATIONS

DESCRIPTION

PCM1807

SLES147 – SEPTEMBER 2005

Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo A/D Converter

• DVD Recorder

• 24-Bit Delta-Sigma Stereo A/D Converter

• Digital TV

• Single-Ended Voltage Input: 3 Vp-p

• AV Amplifier/Receiver

• Oversampling Decimation Filter:

• MD Player

– Oversampling Frequency: × 64

• CD Recorder

– Pass-Band Ripple: ±0.05 dB

• Multitrack Receiver

– Stop-Band Attenuation: –65 dB

• Electric Musical Instrument

– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)

• High Performance:

– THD+N: –93 dB (Typical)

The PCM1807 is high-performance, low-cost,

– SNR: 99 dB (Typical)

single-chip stereo analog-to-digital converter with

single-ended analog voltage input. The PCM1807

– Dynamic Range: 99 dB (Typical)

uses a delta-sigma modulator with 64-times

• PCM Audio Interface With SPI Control:

oversampling and includes a digital decimation filter

– Master/Slave Mode Selectable

and high-pass filter that removes the dc component

of the input signal. For various applications, the

– Data Formats: 24-Bit Left-Justified, 24-Bit

PCM1807 supports master and slave mode and two

data formats in serial audio interface.

• Multiple Functions with SPI Control:

The PCM1807 has many functions which are con-

– Power Down

trolled through SPI serial-control port: power down,

– Mute with Fade-Out and Fade-In

fade-in and fade-out, polarity control, etc.

– Polarity Control

The PCM1807 is suitable for wide variety of

• Analog Antialias LPF Included

cost-sensitive consumer applications where good per-

• Sampling Rate: 16–96 kHz

formance and operation with a 5-V analog supply and

3.3-V digital supply is required. The PCM1807 is

• System Clock: 256 f

, 384 f

, 512 f

fabricated using a highly advanced CMOS process

• Dual Power Supplies:

and is available in a small, 14-pin TSSOP package.

– 5-V for Analog

– 3.3-V for Digital

• Package: 14-Pin TSSOP

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

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PCM1807 SLES147 – SEPTEMBER 2005 Single-Ended, Analog-Input 24-Bit, 96-kHz Stereo A/D Converter FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 24-Bit Delta-Sigma Stereo A/D Converter Single-Ended Voltage Input: 3 Vp-p Oversampling Decimation Filter: – Oversampling Frequency: ×64 – Pass-Band Ripple: ±0.05 dB – Stop-Band Attenuation: –65 dB – On-Chip High-Pass Filter: 0.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN Resolution TYP MAX 24 UNIT Bits DATA FORMAT I2S, left-justified Audio data interface format Audio data bit length 24 Audio data format fS Sampling frequency System clock frequency Bits MSB-first, 2s complement 16 48 96 256 fS 4.096 12.288 24.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL FILTER PERFORMANCE Pass band 0.454 fS Stop band 0.583 fS ±0.05 Pass-band ripple Stop-band attenuation –65 Delay time dB dB 17.4/fS HPF frequency response –3 dB 0.
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PCM1807 www.ti.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 Functional Block Diagram Antialias LPF VINL VREF Delta-Sigma Modulator BCK ×1/64 Decimation Filter with High-Pass Filter Reference Antialias LPF VINR DOUT MS Mode/ Format Control MC Delta-Sigma Modulator MD Clock and Timing Control Power Supply VCC LRCK Serial Interface AGND DGND SCKI VDD B0004-08 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. DECIMATION FILTER FREQUENCY RESPONSE (Continued) PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 0 −1 −2 −3 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 −0.6 −4 –4.13 dB at 0.5 fS −5 −6 −7 −8 −0.8 −9 −1.0 0.0 0.1 0.2 0.3 0.4 0.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 TYPICAL PERFORMANCE CURVES (Continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless otherwise noted. OUTPUT SPECTRUM (Continued) THD+N − Total Harmonic Distortion + Noise − dB THD+N vs SIGNAL LEVEL 0 −10 −20 −30 −40 −50 −60 −70 −80 −90 −100 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level − dB G015 Figure 15.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SYSTEM CLOCK The PCM1807 supports 256 fS, 384 fS and 512 fS as system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 6). The PCM1807 has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, or 512 fS in slave mode.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 Fade-Out Start Fade-In Complete Fade-In Start DOUT (Contents) Fade-Out Complete BPZ 48/fin or 48/fS 48/fin or 48/fS T0080-01 Figure 18. Fade-In and Fade-Out Operations POWER ON The PCM1807 has an internal power-on-reset circuit, and initialization (reset) is performed automatically when the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical), and for 1024 system-clock counts after VDD > 2.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 CLOCK-HALT RESET FUNCTIONS The PCM1807 has a reset function, which is triggered by halting SCKI (pin 6) in both master and slave modes. The function is available anytime after power on. Reset and power down are performed automatically 4 µs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1807 stays in the reset and power-down mode, and DOUT is forced to zero. Also, all registers except the mode control registers are reset once.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SERIAL AUDIO DATA INTERFACE The PCM1807 interfaces the audio system through LRCK (pin 7), BCK (pin 8), and DOUT (pin 9). INTERFACE MODE The PCM1807 supports master mode and slave mode as interface modes, which are selected by MD1 and MD0. MD1 and MD0 are controlled through the serial control port as shown in Table 2.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 FORMAT 0: FMT = 0 24-Bit, MSB-First, I2S Left-Channel LRCK Right-Channel BCK DOUT 1 2 3 22 23 24 MSB 1 LSB 2 3 22 23 24 MSB LSB FORMAT 1: FMT = 1 24-Bit, MSB-First, Left-Justified Left-Channel LRCK Right-Channel BCK DOUT 1 2 MSB 3 22 23 24 LSB 1 2 MSB 3 22 23 24 1 LSB T0016-14 Figure 21.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 INTERFACE TIMING Figure 22 and Figure 23 illustrate the interface timing in slave mode and master mode, respectively. t(LRCP) 1.4 V LRCK t(BCKL) t(BCKH) t(LRSU) t(LRHD) 1.4 V BCK t(BCKP) t(CKDO) t(LRDO) 0.5 VDD DOUT T0017-02 SYMBOL PARAMETER t(BCKP) BCK period t(BCKH) t(BCKL) t(LRSU) MIN TYP MAX UNIT 1/(64 fS) ns BCK pulse duration, HIGH 1.5 × tSCKI ns BCK pulse duration, LOW 1.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(BCKP) t(CKDO) t(LRDO) 0.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1807 operates under LRCK, synchronized with system clock SCKI. The PCM1807 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 FUNCTION CONTROL The PCM1807 has the following functions which can be controlled through the serial control port. When the LRCK (fS), SCKI, MD[1:0], or FMT bit is changed on the fly, a clock-halt reset or an immediate reset by PDWN or SRST via the serial control port is recommended to obtain stable analog performance. MUTE The MUTE bit controls fade-in and fade-out operation for DOUT.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 POWER DOWN The PDWN bit controls the operation of the PCM1807. During power-down mode, both supply current for the analog section and clock signal for the digital section are shut down, and DOUT is forced to zero. Also, all registers except the mode control registers are reset once. The PCM1807 minimizes power dissipation during the power-down mode.
PAGE 21
PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SYSTEM RESET The SRST bit controls the entire ADC operation except fade-out. DOUT is forced to zero immediately and the PCM1807 goes into power-down state. Also, all registers except the mode control register are reset once. The PCM1807 minimizes power dissipation during the power-down state. When the PCM1807 powers up, the digital output is valid after the reset state is released and the time of 1024 SCKI + 8960/fS has elapsed.
PAGE 22
PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 SPI SERIAL CONTROL PORT FOR MODE CONTROL The user-programmable built-in functions of the PCM1807 can be controlled through the serial control port with SPI format. All operations for the serial control port use 16-bit data words. Figure 28 shows the control data word format. The most-significant bit must be set to 0. Seven bits, labeled IDX[6:0], set the register index (or address) for the write operations.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 CONTROL INTERFACE TIMING REQUIREMENTS Figure 30 illustrates a detailed timing diagram for the serial control port. These timing parameters are critical for proper control port operation. t(MHH) MS 1.4 V t(MSS) t(MCL) t(MCH) t(MSH) MC 1.4 V t(MCY) LSB MD 1.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 MODE CONTROL REGISTER The user-programmable mode control functions and the mode control register bit map are shown in Table 9 and Table 10. Table 9.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 APPLICATION INFORMATION TYPICAL CIRCUIT CONNECTION DIAGRAM Figure 31 is typical circuit connection diagram. The antialiasing low-pass filters are integrated on the analog inputs, VINL and VINR. If the performance of these filters is not adequate for an application, appropriate external antialiasing filters are needed. A passive RC filter (100 Ω and 0.01 µF to 1 kΩ and 1000 pF) generally is used. PCM1807 C5(3) C4(2) 4 µs (min) 5V 3.
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PCM1807 www.ti.com SLES147 – SEPTEMBER 2005 APPLICATION INFORMATION (continued) VREF PIN To ensure low source impedance of the ADC references, 0.1-µF ceramic and 10-µF electrolytic capacitors are recommended between VREF and AGND. These capacitors should be located as close as possible to the VREF pin to reduce dynamic errors on the ADC references.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1807PWR Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1807PWR TSSOP PW 14 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.