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FEATURES

APPLICATIONS

DESCRIPTION

PCM1850A

PCM1851A

SLES173 – MARCH 2006

24-BIT, 96-kHz STEREO A/D CONVERTER

WITH 6 × 2-CHANNEL MUX AND PGAE

• PCM Audio Interface

• Multiplexer and Programmable-Gain Amplifier – Master/Slave Mode Selectable

(PGA)

– Data Formats: 24-Bit Left-Justified, 24-Bit

– 6 × 2-Channel Single-Ended Inputs I

S, 16-, 24-Bit Right-Justified

– Multiplexed Output • Mode Control by Serial Interface:

– Maximum Input Level: 2.4 V rms – With SPI Control (PCM1850A)

– Input Resistance: 50 k Ω , Minimum – With I

C Control (PCM1851A)

– PGA Gain: 11-dB to –11-dB Range, 0.5 • Sampling Rate: 16–96 kHz

dB/Step

• System Clock: 256 f

, 384 f

, 512 f

, 768 f

• 24-Bit Delta-Sigma Stereo A/D Converter

• Dual Power Supplies: 5 V for Analog, 3.3 V for

• Antialiasing Filter Included Digital

• Oversampling Decimation Filter • Package: 32-Pin TQFP

– Oversampling Frequency: × 64

– Pass-Band Ripple: ± 0.05 dB

• DVD/HDD/DVD+HDD Recorder

– Stop-Band Attenuation: –65 dB

• AV Amplifier Receiver

– On-Chip High-Pass Filter: 0.91 Hz (48 kHz)

• CD Recorder

• High Performance

• MD Recorder

– THD+N: 0.0023% (Typically)

• Multitrack Recorder

– SNR: 101 dB (Typically)

• Electric Musical Instrument

– Dynamic Range: 102 dB (Typically)

The PCM1850A/1851A is a high-performance, low-cost, single-chip stereo analog-to-digital converter with a

single-ended analog front end that consists of a 6-stereo-input multiplexer and wide-range PGA. The

PCM1850A/1851A includes a delta-sigma modulator with 64-times oversampling, a digital decimation filter and a

low-cut filter that removes the dc component of the input signal. For various applications, the PCM1850A/1851A

supports two modes (master and slave) and four data formats through a serial control interface, SPI for the

PCM1850A and I

C for the PCM1851A. The PCM1850A/1851A is suitable for a wide variety of cost-sensitive

DVD/CD/MD recorder and receiver applications where good performance and operation from a 5-V analog

supply and 3.3-V digital supply is required. The PCM1850A/1851A is fabricated using a highly advanced CMOS

process and is available in a small 32-pin TQFP package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

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PCM1850A PCM1851A SLES173 – MARCH 2006 24-BIT, 96-kHz STEREO A/D CONVERTER WITH 6 × 2-CHANNEL MUX AND PGAE FEATURES • • • • • Multiplexer and Programmable-Gain Amplifier (PGA) – 6×2-Channel Single-Ended Inputs – Multiplexed Output – Maximum Input Level: 2.4 V rms – Input Resistance: 50 kΩ, Minimum – PGA Gain: 11-dB to –11-dB Range, 0.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 TERMINAL FUNCTIONS PCM1850A TERMINAL I/O DESCRIPTION NAME NO.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 PCM1851A TERMINAL NAME NO.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC VDD Supply voltage VALUE UNIT –0.3 to 6.5 V –0.3 to 4 V ±0.1 V –0.3 to (VDD + 0.3) < 4 V –0.3 to 6.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS PCM1850APJT, PCM1851APJT MIN TYP UNIT MAX INPUT LOGIC VIH (1) VIL (1) VIH (2) (3) VIL IIH Input logic level (2) (3) (2) IIL (2) IIH (1) (3) 2 VDD 0 0.8 2 5.5 0 0.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS PCM1850APJT, PCM1851APJT MIN TYP UNIT MAX ACCURACY Gain mismatch, channel-to-channel Gain error Bipolar zero error DYANAMIC PERFORMANCE THD+N % of FSR ±2 ±5 % of FSR % of FSR (1) (2) fS = 48 kHz, VIN = –0.5 dB (1.89 Vrms) 0.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted) PARAMETER TEST CONDITIONS PCM1850APJT, PCM1851APJT MIN TYP UNIT MAX POWER-SUPPLY REQUIREMENTS VCC VDD Voltage range 4.5 5 5.5 2.7 3.3 3.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted). DIGITAL FILTER Decimation Filter Frequency Response AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0 50 −10 −20 0 Amplitude – dB Amplitude – dB −30 −50 −100 −40 −50 −60 −70 −150 −80 −90 −200 0 8 16 Frequency [× fS] 24 −100 0.00 32 0.25 0.50 0.75 1.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted). High-Pass Filter Frequency Response AMPLITUDE vs FREQUENCY AMPLITUDE vs FREQUENCY 0.2 0 −10 −20 −30 −0.2 Amplitude – dB Amplitude – dB 0.0 −0.4 −0.6 −40 −50 −60 −70 −80 −0.8 −90 −100 0.0 −1.0 0 1 2 3 4 Frequency [× fS/1000] 0.1 0.2 0.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted). TOTAL HARMONIC DISTORTION + NOISE vs FREE-AIR TEMPERATURE DYNAMIC RANGE AND SNR vs FREE-AIR TEMPERATURE 107 106 Dynamic Range and SNR – dB THD+N – Total Harmonic Distortion + Noise – % 0.004 0.003 0.002 104 103 Dynamic Range 102 SNR 101 100 99 98 0.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted). TOTAL HARMONIC DISTORTION + NOISE vs fSAMPLE CONDITION DYNAMIC RANGE AND SNR vs fSAMPLE CONDITION 107 106 Dynamic Range and SNR – dB THD+N – Total Harmonic Distortion + Noise – % 0.004 0.003 0.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 TYPICAL PERFORMANCE CURVES AT PGA GAIN = –5.5 dB (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 256 fS, 24-bit data (unless otherwise noted). TOTAL HARMONIC DISTORTION + NOISE vs SIGNAL LEVEL THD+N – Total Harmonic Distortion + Noise – % 100 10 1 0.1 0.01 0.001 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 Signal Level – dB G017 Figure 17.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 DETAILED DESCRIPTION SYSTEM CLOCK The PCM1850A/1851A supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI (pin 7). The PCM1850A/1851A has a system clock detection circuit which automatically senses if the system clock is operating at 256 fS, 384 fS, 512 fS, or 768 fS in slave mode.
PAGE 15
PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 POWER-ON-RESET SEQUENCE The PCM1850A/1851A has an internal power-on-reset circuit, and initialization (reset) is performed automatically at the time that the power supply (VDD) exceeds 2.2 V (typical). While VDD < 2.2 V (typical) and for 1024 system clocks after VDD > 2.2 V (typical), the PCM1850A/1851A stays in the reset state and the digital output is forced to zero.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 ANALOG FRONT END The PCM1850A/1851A has a built-in analog front-end circuit, which is shown in the block diagram of Figure 22. Selection of the multiplexer input and PGA gain is controlled by mode control via the serial port as shown in Table 2 and Table 3. The change of the input selection and the gain selection is performed immediately after the serial control packet for the change is sent.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 Table 3. PGA Gain Selection PG5 PG4 PG3 PG2 PG1 PG0 PGA GAIN [dB] RIN [kΩ, Typical] (1) 0 0 1 0 1 0 –11 (default) 201 0 0 1 0 1 1 –10.5 199 0 0 1 1 0 0 –10 196 0 0 1 1 0 1 –9.5 193 0 0 1 1 1 0 –9 190 0 0 1 1 1 1 –8.5 188 0 1 0 0 0 0 –8 185 0 1 0 0 0 1 –7.5 181 0 1 0 0 1 0 –7 178 0 1 0 0 1 1 –6.5 175 0 1 0 1 0 0 –6 172 0 1 0 1 0 1 –5.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 SERIAL AUDIO DATA INTERFACE The PCM1850A/1851A interfaces with the audio system through BCK (pin 2), LRCK (pin 1), and DOUT (pin 3). Interface Mode The PCM1850A/1851A supports both master and slave modes as interface modes, and they are selected by mode control via the serial port as shown in Table 4.
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PCM1850A PCM1851A www.ti.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 Interface Timing Figure 24 and Figure 25 illustrate the interface timing in slave and master modes, respectively. t(LRCP) 1.4 V LRCK t(BCKL) t(LRSU) t(BCKH) t(LRHD) 1.4 V BCK t(CKDO) t(BCKP) t(LRDO) 0.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 t(LRCP) 0.5 VDD LRCK t(BCKL) t(BCKH) t(CKLR) 0.5 VDD BCK t(CKDO) t(BCKP) t(LRDO) 0.5 VDD DOUT T0018-02 SYMBOL PARAMETER t(BCKP) BCK period t(BCKH) BCK pulse duration, HIGH t(BCKL) BCK pulse duration, LOW t(CKLR) Delay time, BCK falling edge to LRCK valid t(LRCP) LRCK period t(CKDO) Delay time, BCK falling edge to DOUT valid t(LRDO) Delay time, LRCK edge to DOUT valid MIN TYP MAX UNIT 150 1/(64 fS) 1000 ns 60 0.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1850A/1851A operates under LRCK, synchronized with system clock SCKI. The PCM1850A/1851A does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 System Reset Control The system reset control is used to resynchronize the system via the serial port when the system clock frequency, interface mode, and data format are changed. Change them while SRST = LOW. If they are changed during normal operation, analog performance can be degraded.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 CONTROL INTERFACE TIMING REQUIREMENTS (PCM1850A) Figure 29 shows a detailed timing diagram for the serial control interface of the PCM1850A. These timing parameters are critical for proper control port operation. t(MHH) MS 1.4 V t(MSS) t(MCL) t(MCH) t(MSH) MC 1.4 V t(MCY) LSB MD 1.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 SDA SCL St 1−7 8 9 1−8 9 1−8 9 9 Slave Address R/W ACK DATA ACK DATA ACK ACK Start Condition Sp R/W: Read Operation if 1; Otherwise, Write Operation ACK: Acknowledgement of a Byte if 0 DATA: 8 Bits (Byte) Stop Condition Transmitter M M M S M S M S S M Data Type St Slave Address R/W ACK DATA ACK DATA ACK ACK Sp M: Master Device St: Start Condition S: Slave Device Sp: Stop Condition T0049-05 2 Figure 30.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 TIMING DIAGRAM Start Repeated Start Stop t(D-HD) t(BUF) t(D-SU) t(SDA-F) t(P-SU) t(SDA-R) SDA t(SCL-R) t(RS-HD) t(LOW) SCL t(S-HD) t(HI) t(RS-SU) t(SCL-F) T0050-01 SYMBOL PARAMETER MIN UNIT 100 kHz f(SCL) SCL clock frequency t(BUF) Bus free time between STOP and START conditions 4.7 µs t(LOW) Low period of the SCL clock 4.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 MODE CONTROL REGISTERS User-Programmable Mode Control Functions The PCM1850A/1851A has several user-programmable functions which are accessed via control registers. The registers are programmed using the serial control port which is discussed in the SPI Serial Control Port for Mode Control (PCM1850A) and I 2C Serial Control Port for Mode Control (PCM1851A) sections of this data sheet.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 APPLICATION INFORMATION TYPICAL CIRCUIT CONNECTION DIAGRAM The following figure illustrates a typical circuit connection diagram for six stereo inputs and an analog monitor.
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PCM1850A PCM1851A www.ti.com SLES173 – MARCH 2006 APPLICATION INFORMATION (continued) BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD Pins The digital and analog power supply lines to the PCM1850A/1851A must be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM1851APJTR Package Package Pins Type Drawing TQFP PJT 32 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 16.8 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1851APJTR TQFP PJT 32 1000 346.0 346.0 33.
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MECHANICAL DATA MPQF112 – NOVEMBER 2001 PJT (S-PQFP–N32) PLASTIC QUAD FLATPACK 0,45 0,30 0,80 0,20 M 0,20 0,09 Gage Plane 32 0,15 0,05 1 0,25 0°– 7° 7,00 SQ 0,75 0,45 9,00 SQ 1,05 0,95 Seating Plane 0,10 1,20 1,00 4203540/A 11/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.