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FEATURES

APPLICATIONS

DESCRIPTION

PCM1870

SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007

16-Bit Low-Power Stereo Audio ADC With Microphone Bias and Microphone Amplifier

• Package:

• Analog Front End: – 24-QFN (4 mm × 5 mm)

– Stereo Single End Input With MUX – 24-DSBGA (2.49 mm × 3.49 mm)

– Mono Differential Input • Operation Temperature Range: – 40 ° C to 85 ° C

– Stereo Programmable Gain Amplifier

– Microphone Boost Amplifier and Bias

• Portable Audio Player, Cellular Phone

• Analog Performances Dynamic Range: 90 dB

• Video Camcorder, Movie Digital Still Camera

• Power-Supply Voltage

• PMP/DMB, Voice Recorder

– 1.71 V to 3.6 V for Digital I/O Section

– 1.71 V to 3.6 V for Digital Core Section

– 2.4 V to 3.6 V for Analog Section

The PCM1870 is a low-power stereo ADC designed

• Low Power Dissipation:

for portable digital audio applications, with line-input

amplifier, boost amplifier, microphone bias,

– 13 mW in Record, 1.8/2.4 V, 48 kHz, Stereo

programmable gain control, sound effects, and auto

– 5.3 mW in Record, 1.8/2.4 V, 8 kHz, Mono

level control (ALC). It is available in 24-QFN (4-mm ×

– 3.3 μ W in All Power Down

5-mm) and 24-DSBGA (2.49-mm × 3.49-mm)

packages to save footprint. The PCM1870 accepts

• Sampling Frequency: 5 kHz to 50 kHz

right-justified, left-justified, I

S, and DSP formats,

• Auto Level Control for Recording

providing easy interfacing to audio DSP and encoder

• Operation by Single Clock Input Without PLL

chips. Sampling rates up to 50 kHz are supported.

The user-programmable functions are accessible

• System Clock: Common Audio Clock

through a 2- or 3-wire serial control port.

(256 f

/384 f

), 12/24, 13/26, 13.5/27, 19.2/38.4,

19.68/39.36 MHz

• 2 (I

C) or 3 (SPI) Wire Serial Control

• Programmable Function by Register Control:

– Digital Soft Mute

– Power Up/Down Control for Each Module

– 30-dB to – 12-dB Gain for Analog Inputs

– 0/12/20-dB Boost for Microphone Input

– Parameter Settings for ALC

– Three-Band Tone Control and 3D Sound

– High-Pass Filter and Two-Stage Notch Filter

• Pop Noise Reduction Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (54 pages)

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PCM1870 SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 16-Bit Low-Power Stereo Audio ADC With Microphone Bias and Microphone Amplifier FEATURES 1 • • • • • • • • • • • Analog Front End: – Stereo Single End Input With MUX – Mono Differential Input – Stereo Programmable Gain Amplifier – Microphone Boost Amplifier and Bias Analog Performances Dynamic Range: 90 dB Power-Supply Voltage – 1.71 V to 3.6 V for Digital I/O Section – 1.71 V to 3.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS, and 16-bit data, unless otherwise noted PARAMETER TEST CONDITIONS PCM1870RHF, PCM1870YZF MIN TYP MAX UNIT FILTER CHARACTERISTICS Decimation Filter for ADC Pass band 0.408 fS Stop band 0.591 fS Pass-band ripple Stop-band attenuation ±0.02 f < 3.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 8 kHz to 48 kHz, system clock = 256 fS and 16-bit data, unless otherwise noted. DECIMATION FILTER, STOP-BAND DECIMATION FILTER, PASS-BAND 0 0.2 –20 Amplitude – dB Amplitude – dB 0.1 –40 –60 –80 0 –0.1 –100 –120 –0.2 0 1 2 Frequency [´ fS ] 3 4 0 0.1 0.2 0.3 Frequency [´ fS ] 0.4 G001 G002 Figure 1. Figure 2.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 8 kHz to 48 kHz, system clock = 256 fS and 16-bit data, unless otherwise noted. HIGH-PASS FILTER PASS-BAND CHARACTERISTICS (fC = 240 Hz at 48 kHz) 5 Amplitude – dB 0 –5 –10 –15 –20 0 0.01 0.02 Frequency [´ fS ] 0.03 0.04 G004 Figure 5.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 44.1 kHz, system clock = 256 fS and 16-bit data, unless otherwise noted. 3 BAND TONE CONTROL (BASS) 15 10 10 5 5 Amplitude – dB Amplitude – dB 3 BAND TONE CONTROL (BASS, MID, TREBLE) 15 0 –5 –10 0 –5 –10 –15 0.01 –15 0.1 1 10 100 Frequency – Hz 1k 10k 100k 0 400 600 Frequency – Hz 200 800 G005 G006 Figure 6.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VDD = VIO = VCC = VPA = 3.3 V, fS = 48 kHz, system clock = 256 fS and 16-bit data, unless otherwise noted.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 PCM1870 DESCRIPTION Analog Input The AIN1L, AIN1R, AIN2L and AIN2R pins can be used as microphone or line inputs with selectable 0- or 20-dB boost and 1-Vrms input. All analog inputs have high input impedance (20 kΩ), which is not changed by gain settings. One pair of inputs is selected by register 87 (AIL[1:0], AIR[1:0]). AIN1L and AIN1R can also be used as a monaural differential input.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Zero-Cross Detection Zero-cross detection minimizes audible zipper noise while changing analog volume and digital attenuation. This function can be applied to digital input or digital output by register 86 (ZCRS). Power Up/Down for Each Module Using register 73 (PBIS), register 82 (PAIR, PAIL, PADS, PMCB, PADR, PADL), and register 90 (PCOM), unused modules can be powered down to minimize power consumption (13 mW when recording only).
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 DESCRIPTION OF OPERATION System Clock Input The PCM1870 can accept input clocks of various frequencies without a PLL. The clocks are used for clocking of the digital filters, auto level control, and delta-sigma modulators, and classified into common-audio and application-specific clocks. Table 2 shows frequencies of the common audio clock and the application-specific clock. Figure 13 shows timing requirements for system clock inputs.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Table 3. Recommended Power-On Sequence (1) (2) (3) STEP REGISTER SETTINGS 1 — 2 5102H ADC audio interface format (left-justified) 3 5A00H PG1, PG2 gain control (0 dB) 4 4980H Analog bias power up 5 5601H Zero-cross detection enable 6 4A01H VCOM power up 7 523FH Analog front end (ADL, ADR, D2S, MCB, PG1, 2, 5, 6) power up 8 5711H Analog input (MUX3, MUX4) select.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Power-Supply Current The current consumption of the PCM1870 depends on the power-up/down status of each circuit module. In order to save power consumption, disabling each module is recommended when it is not used in an appliction or operation. Table 5 shows current consumtption in some states. Table 5. Power Consumption Table POWER SUPPLY CURRENT [mA] OPERATION MODE PD [mW] VDD (1.8 V) VDD (3.3 V) VCC (3.3 V) VIO (3.3 V) TOTAL (VDD = 1.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Audio Serial Interface The audio serial interface of the PCM1870 consists of LRCK, BCK and DOUT. Sampling rate (fS), left and right channel are present on LRCK. DOUT transmits the serial data from the decimation filter for the ADC. BCK is used to transmit the serial audio data on DOUT at its high-to-low transition. BCK and LRCK should be synchronized with audio system clock. Ideally, it is recommended that they are derived from it.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 THREE-WIRE INTERFACE (SPI, MODE (PIN 28) = LOW) All write operations for the serial control port use 16-bit data words. Figure 17 shows the control data word format. The most significant bit must be 0. There are seven bits, labeled IDX[6:0], that set the register address for the write operation. The least-significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Three-Wire Interface (SPI) Timing Requirements Figure 19 shows a detailed timing diagram for the serial control interface. These timing parameters are critical for proper control port operation.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 TWO-WIRE INTERFACE [I2C, MODE (PIN 28) = HIGH] The PCM1870 supports the I2C serial bus and the data transmission protocol for the I2C standard as a slave device. This protocol is explained in I2C specification 2.0. In I2C mode, the control terminals are changed as follows.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Write Operation A master can write any PCM1870 registers using single access. The master sends a PCM1870 slave address with a write bit, a register address, and the data. When undefined registers are accessed, the PCM1870 does not send an acknowledgement. The Figure 21 shows a diagram of the write operation.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Timing Diagram Start Stop t(D-HD) t(BUF) t(SDA-F) t(D-SU) t(SDA-R) t(P-SU) SDA t(SCL-R) t(RS-HD) t(SP) t(LOW) SCL t(S-HD) t(HI) t(RS-SU) t(SCL-F) T0050-03 TIMING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT 100 kHz fSCL SCL clock frequency Standard t(BUF) Bus free time between a STOP and START condition Standard 4.7 μs t(LOW) Low period of the SCL clock Standard 4.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 USER-PROGRAMMABLE MODE CONTROLS Register Map The mode control register map is shown in Table 6. Each register includes an index (or address) indicated by the IDX[6:0] bits. Table 6.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 73 B15 Register 73 0 B14 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 B5 B4 B3 B2 B1 B0 IDX0 PBIS RSV RSV RSV RSV RSV RSV RSV IDX[6:0]: 100 1001b (49h) Register 73 PBIS: Power Up/Down Control for Bias Default value: 0 This bit is used to control power up/down for the analog bias circuit.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 81 B15 Register 81 0 B14 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 IDX0 HPF1 HPF0 B5 B4 RMUL RMUR B3 RSV B2 B1 DSMC RFM1 B0 RFM0 IDX[6:0]: 101 0001b (51h) Register 81 HPF[1:0]: High-Pass Filter Selection Default value: 00 The PCM1870 has a digital high-pass filter to remove dc voltage at the input of the ADC. The cutoff frequency of the high-pass filter can be selected.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 83 B15 Register 83 B14 0 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 B5 B4 B3 B2 B1 B0 IDX0 RALC RSV RRTC RATC RCP1 RCP0 RLV1 RLV0 IDX[6:0]: 1010011b (53h) Register 83 RALC: Automatic Level Control (ALC) Enable for Recording Default value: 0 Auto level control can be enabled with some parameters for microphone input or lower-level analog source.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 MSR[2:0]: System Clock Dividing Rate Selection in Master Mode (Register 70) Default value: 000 These bits are used to set the dividing rate of the input system clock. See Table 8 for details. Table 8. System Clock Frequency for Common Audio Clock SYSTEM CLOCK SCK (MHz) ADC SAMPLING RATE ADC fS (kHz) 6.144 8.192 12.288 18.432 5.6448 11.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Table 9. System Clock Frequency for Application-Specific Audio Clock SYSTEM CLOCK SCK (MHz) ADC SAMPLING RATE ADC fS (kHz) 13.5 27 12 24 19.2 32 DAC SAMPLING RATE DAC fS (kHz) REGISTER SETTING MSR[2:0] NPR[5:0] BIT CLOCK BCK (fS) 48.214 (SCK/280) 010 00 0010 70 44.407 (SCK/304) 010 00 0001 76 32.142 (SCK/420) 010 10 0010 70 24.107 (SCK/560) 100 00 0010 70 22.203 (SCK/608) 100 00 0001 76 16.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Table 9. System Clock Frequency for Application-Specific Audio Clock (continued) SYSTEM CLOCK SCK (MHz) ADC SAMPLING RATE ADC fS (kHz) 38.4 13 26 19.68 39.36 DAC SAMPLING RATE DAC fS (kHz) REGISTER SETTING MSR[2:0] NPR[5:0] BIT CLOCK BCK (fS) 48.484 (SCK/792) 011 01 0110 66 44.444 (SCK/864) 011 01 0101 72 32.323 (SCK/1188) 011 11 0110 66 24.242 (SCK/1584) 101 01 0110 66 22.222 (SCK/1728) 101 01 0101 72 16.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 ZCRS: Zero Cross for Digital Attenuation/Mute and Analog Gain Setting Default value: 0 This bit is used to enable the zero-cross detector, which reduces zipper noise while the digital soft mute or analog gain setting is being changed. If no zero-cross data is input for a 512/fS period (10.6 ms at a 48-kHz sampling rate), then a time-out occurs and the PCM1870 starts changing the attenuation, gain, or volume level.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 90 B15 Register 90 0 B14 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 B5 B4 B3 B2 B1 B0 IDX0 RSV RSV RSV RSV RSV RSV G20R G20L IDX[6:0]: 101 1010b (5Ah) Register 90 G20R: 20-dB Boost for PG2 (Gain Amplifier for AIN1R and AIN2R) Default value: 0 This bit is used to boost the microphone signal when the analog input is small.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 92 B15 Register 92 0 B14 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 B5 B4 B3 B2 B1 B0 IDX0 LPAE RSV RSV LGA4 LGA3 LGA2 LGA1 LGA0 IDX[6:0]: 101 1100b (5Ch) Register 92 LPAE: Automatic Attenuation Setting for Bass Boost Gain Control Default value: 0 A gain setting for bass boost may cause digital data saturation, depending on the input data level.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 93 B15 Register 93 0 B14 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 B5 IDX0 RSV RSV RSV B4 B3 B2 B1 B0 MGA4 MGA3 MGA2 MGA1 MGA0 IDX[6:0]: 101 1101b (5Dh) Register 93 MGA[4:0]: Middle Boost Gain Control Default value: 0 0000 These bits are used to set midrange boost gain level for the digital data. The center frequency for boost is 1 kHz.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 94 B15 Register 94 0 B14 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 B5 B4 B3 B2 B1 B0 IDX0 RSV RSV RSV HGA4 HGA3 HGA2 HGA1 HGA0 IDX[6:0]: 101 1110b (5Eh) Register 94 HGA[4:0]: Treble Boost Gain Control Default value: 0 0000 These bits are used to set treble boost gain level for the digital data. The center frequency for boost is 5 kHz.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 95 B15 Register 95 0 B14 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 B5 B4 B3 B2 B1 B0 IDX0 RSV 3DEN RSV 3FL0 3DP3 3DP2 3DP1 3DP0 IDX[6:0]: 1011111b (5Fh) Register 95 3DEN: 3D Sound Effect Enable Default value: 0 This bit is used for enabling the 3-D sound effect filter. This filter has two independently controlled parameters.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Register 96 B15 Register 96 0 B14 B13 B12 B11 B10 B9 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 B8 B7 B6 B5 B4 B3 B2 B1 B0 IDX0 NEN2 NEN1 NUP2 NUP1 RSV RSV RSV MXEN IDX[6:0]: 110 0000b (60h) Register 96 NEN2: Second-Stage Notch Filter Enable Default value: 0 The PCM1870 has a two-stage notch filter. The two stages can separately set filter characteristics. This bit is used to enable the second stage.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Calculating Filter Coefficients The PCM1870 provides a dual-stage notch filter at the digital output of the ADC. The filter characteristics of each filter stage can be programmed. The characteristics are determined by calculating coefficients for three parameters, sampling frequency, center frequency and bandwidth, as shown in the following equations.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 BOARD DESIGN AND LAYOUT CONSIDERATIONS VCC, VDD, and VIO Pins The digital and analog power supply lines to the PCM1870 should be bypassed to the corresponding ground pins with 0.1- to 4.7-μF ceramic capacitors or electrolytic capacitors, placed as close to the pins as possible to maximize the dynamic performance of ADC.
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PCM1870 www.ti.com SLAS544A – MAY 2007 – REVISED SEPTEMBER 2007 Changes from Original (May 2007) to Revision A ........................................................................................................... Page • • • • • Added new package in FEATURES section.......................................................................................................................... 1 Added new package in DESCRIPTION section ........................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM1870RHFR VQFN RHF 24 3000 330.0 12.4 4.3 5.3 1.3 8.0 12.0 Q1 PCM1870RHFT VQFN RHF 24 250 180.0 12.4 4.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM1870RHFR VQFN RHF 24 3000 367.0 367.0 35.0 PCM1870RHFT VQFN RHF 24 250 210.0 185.0 35.
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D: Max = 3.48 mm, Min = 3.42 mm E: Max = 2.48 mm, Min = 2.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.