Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsPCM3001E

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FEATURES

APPLICATIONS

DESCRIPTION

Lch In

Rch In

Analog Front-End

Delta-Sigma

Modulator

Digital

Decimation

Filter

Serial Interface

and

Mode Control

Digital Out

Mode Control

System Clock

B0006-03

Digital In

Digital

Interpolation

Filter

Lch Out

Rch Out

Low-Pass Filter

and

Output Buffer

Multilevel

Delta-Sigma

Modulator

PCM3000

PCM3001

SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004

18-BIT STEREO AUDIO CODEC, SINGLE-ENDED ANALOG INPUT/OUTPUT

• Single 5-V Power Supply

• Monolithic 18-Bit ∆ Σ ADC and DAC

• Small Package: SSOP-28

• 16- or 18-Bit Input/Output Data

• Accepts Seven Alternate Formats

• Sampling Keyboards

• Stereo ADC:

• Digital Mixers

– Single-Ended Voltage Input

• Mini-Disk Recorders

– 64 × Oversampling Digital Filter

• Hard-Disk Recorders

• Pass-Band Ripple: ± 0.05 dB

• Karaoke Systems

• Stop-Band Attenuation: –65 dB

• DSP-Based Car Stereo

– High Performance:

• DAT Recorders

• THD+N: –88 dB

• Video Conferencing

• SNR: 94 dB

• Dynamic Range: 94 dB

– Digital High-Pass Filter The PCM3000/3001 is a low-cost, single-chip stereo

audio codec (analog-to-digital and digital-to-analog

• Stereo DAC

converter) with single-ended analog voltage input and

– Single-Ended Voltage Outut

output.

– Analog Low-Pass Filter

Both ADCs and DACs employ delta-sigma modu-

– 8 × Oversampling Digital Filter

lation with 64-times oversampling. The ADCs include

• Pass-Band Ripple: ± 0.17 dB a digital decimation filter and the DACs include an

8-times oversampling digital interpolation filter. The

• Stop-Band Attenuation: 35 dB

DACs also include digital attenuation, de-emphasis,

– High Performance:

infinite zero detection and soft mute to form a

• THD+N: –90 dB

complete subsystem. The PCM3000/3001 operates

with left-justified, right-justified, I

S or DSP data

• SNR: 98 dB

formats.

• Dynamic Range: 97 dB

The PCM3000 can be programmed with a three-wire

• Special Features (PCM3000)

serial interface for special features and data formats.

– Digital De-Emphasis

The PCM3001 can be pin-programmed for data

– Digital Attenuation (256 Steps)

formats.

– Soft Mute

The PCM3000 and PCM3001 are fabricated using a

– Digital Loopback highly advanced CMOS process and are available in

a small 28-pin SSOP package. The PCM3000/3001

• Sample Rate: 4 kHz to 48 kHz

are suitable for a wide variety of cost-sensitive

• System Clock: 256 f

, 384 f

, 512 f

consumer applications where good performance is

required.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

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PCM3000 PCM3001 SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 18-BIT STEREO AUDIO CODEC, SINGLE-ENDED ANALOG INPUT/OUTPUT FEATURES • • • • • • • • Monolithic 18-Bit ∆Σ ADC and DAC 16- or 18-Bit Input/Output Data Accepts Seven Alternate Formats Stereo ADC: – Single-Ended Voltage Input – 64× Oversampling Digital Filter • Pass-Band Ripple: ±0.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX f = 1 kHz, VIN = –0.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 5 V, fS = 44.1 kHz, SYSCLK = 384 fS, CLKIO input, and 18-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Output Voltage range Center voltage Load impedance AC load 0.62 VCC Vp-p 0.5 VCC VDC 5 kΩ Analog Low-Pass Filter Frequency response f = 20 kHz –0.16 dB POWER SUPPLY REQUIREMENTS VCC 4.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Analog supply voltage, VCC1, VCC2 4.5 5 5.5 VDC Digital supply voltage, VDD 4.5 5 5.5 VDC Analog input voltage, full scale (–0 dB) 2.9 Digital input logic family Digital input clock frequency Analog output load resistance System clock Sampling clock 8.192 24.
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PCM3000 PCM3001 www.ti.
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PCM3000 PCM3001 www.ti.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF ADC SECTION All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, VIN = 2.9 Vp-p, and SYSCLK = 384 fS, unless otherwise noted 3 0.006 2 FS 0.004 1 0.002 −25 0 25 50 75 0 100 TA − Free-Air Temperature − °C −60 dB 0.008 3 0.006 2 0.004 1 FS 0.002 4.25 4.50 4.75 5.00 5.25 G002 SNR AND DYNAMIC RANGE vs POWER SUPPLY 44.1 kHz 3 0.008 −60 dB 0.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF ADC SECTION (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, VIN = 2.9 Vp-p, and SYSCLK = 384 fS, unless otherwise noted THD+N vs OUTPUT DATA RESOLUTION 4 0.008 THD+N − Total Harm. Dist. + Noise at −60 dB − % THD+N − Total Harm. Dist. + Noise at FS − % 0.010 3 −60 dB 0.006 2 FS 0.004 1 0.002 0 16-Bit 18-Bit Resolution G005 Figure 5.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF DAC SECTION (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, fIN = 1 kHz, fS = 44.1 kHz, 18-bit data, and SYSCLK = 384 fS, unless otherwise noted 3 0.008 48 kHz 0.006 2 −60 dB 48 kHz 44.1 kHz 0.004 1 FS 44.1 kHz 0.002 100 Dynamic Range 384 fS 98 98 SNR 96 96 94 94 92 4.25 0 256 fS 100 512 fS 4.50 4.75 5.00 5.25 VCC − Supply Voltage − V System Clock G008 Figure 8.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted DECIMATION FILTER OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS 0 0 −20 Amplitude − dB −100 −40 −60 −150 −80 −200 0 8 16 24 −100 0.0 32 Normalized Frequency [× fS Hz] 0.2 0.4 0.6 0.8 Normalized Frequency [× fS Hz] G011 Figure 11. 1.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted HIGH-PASS FILTER HIGH-PASS FILTER RESPONSE 0.2 Amplitude − dB 0.0 −0.2 −0.4 −0.6 −0.8 −1.0 0 1 2 3 4 Normalized Frequency [× fS/1000 Hz] G014 Figure 14.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted DIGITAL FILTER PASS-BAND RIPPLE CHARACTERISTIC 0.0 −20 −0.2 −40 −0.4 Level − dB Level − dB OVERALL FREQUENCY CHARACTERISTIC 0 −60 −80 −0.6 −0.8 −100 −1.0 0 0.4536 fS 1.3605 fS 2.2675 fS 3.1745 fS 4.0815 fS 0 0.1134 fS f − Frequency − Hz 0.2268 fS 0.3402 fS 0.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted DE-EMPHASIS ERROR (44.1 kHz) 0.6 −2 0.4 −4 0.2 Error − dB Level − dB DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) 0 −6 0.0 −8 −0.2 −10 −0.4 −12 −0.6 0 5k 10k 15k 20k 25k 0 4999.8375 f − Frequency − Hz 9999.675 14999.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 5 V, and SYSCLK = 384 fS, unless otherwise noted ANALOG LOW-PASS FILTER INTERNAL ANALOG FILTER FREQUENCY RESPONSE (20 Hz–24 kHz, EXPANDED SCALE) INTERNAL ANALOG FILTER FREQUENCY RESPONSE (10 Hz–10 MHz) 10 1.0 5 0 −5 0.5 −10 Level − dB Level − dB −15 0.0 −20 −25 −30 −35 −40 −0.5 −45 −50 −55 −1.
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PCM3000 PCM3001 www.ti.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 470 pF CINPL 10 2.2 µF + 1 VINL 9 CINNL 15 kΩ − − 1 kΩ + (+) + 1 kΩ 4 4.7 µF (−) Delta-Sigma Modulator VREFL + VREF S0011-04 Figure 17. Analog Front-End (Single-Channel) PCM AUDIO INTERFACE The four-wire digital audio interface for the PCM3000/3001 is on LRCIN (pin 16), BCKIN (pin 17), DIN (pin 18), and DOUT (pin 19). The PCM3000/3001 can operate with seven different data formats.
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PCM3000 PCM3001 www.ti.
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PCM3000 PCM3001 www.ti.
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PCM3000 PCM3001 www.ti.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 FORMAT 6: FMT[2:0] = 110 DAC: 16-Bit, MSB-First, DSP-Frame LRCIN Left-Channel Right-Channel BCKIN DIN 16 1 2 3 14 15 16 1 MSB 2 3 14 15 16 1 LSB MSB LSB ADC: 16-Bit, MSB-First, DSP-Frame Left-Channel LRCIN Right-Channel BCKIN DOUT 16 1 2 MSB 3 14 15 16 1 2 3 LSB MSB 14 15 16 1 LSB T0016-10 Figure 21.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 t(LRP) 1.4 V LRCIN t(BCL) t(BCH) t(LB) t(BL) 1.4 V BCKIN t(BCY) t(DIS) t(DIH) 1.4 V DIN t(BDO) t(LDO) 0.
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PCM3000 PCM3001 www.ti.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Table 1. System Clock Frequencies SAMPLING RATE FREQUENCY (kHz) SYSTEM CLOCK FREQUENCY (MHz) 256 fS 384 fS 512 fS 32 8.1920 12.2880 16.3840 44.1 11.2896 16.9344 22.5792 48 12.2880 18.4320 24.5760 t(CLKIH) XTI CLKIO 3.2 V 2.0 V 1.4 V 0.8 V XTI or CLKIO t(CLKIL) T0005-06 System clock pulse duration, HIGH t(CLKIH) 12 ns (min) System clock pulse duration, LOW t(CLKIL) 12 ns (min) Figure 24.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Reset Removal or Power Down(1) Off Reset Internal Reset Ready/Operation 32/fS DAC VOUT VCOM (0.5 VCC2) 4096/fS ADC DOUT Zero Data Zero Data Normal Data(2) T0019-03 (1) Power down is for PCM3000 only. (2) The HPF transient response (exponentially attenuated signal from ±1.5% dc with 200-ms time constant) appears initially. Figure 26.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Resynchronization Synchronization Lost Synchronous State of Synchronization Asynchronous Synchronous Within 1/fS DAC VOUT 22.2/fS VCOM (0.5 VCC2) Undefined Data Normal Data Undefined Data Normal Data 32/fS ADC DOUT Undefined Data Normal Data Normal Data(1) Zero Data T0020-04 (1) The HPF transient response (exponentially attenuated signal from ±1.5% dc with 200-ms time constant) appears initially. Figure 28.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 t(MHH) t(MLH) t(MLS) 1.4 V ML t(MCL) t(MLL) t(MCH) 1.4 V MC t(MCY) LSB MD 1.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Table 3.
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PCM3000 PCM3001 www.ti.com AL[7:0]: SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Bits 7:0 – DAC Attenuation Data for Left Channel AL7 and AL0 are the MSB and LSB, respectively. The attenuation level (ATT) is given by ATT = 20 × log10 (AL[7:0]/256) (dB), except AL[7:0] = FFh AL[7:0] ATTENUATION LEVEL 00h – ∞ dB (mute) 01h –48.16 dB : : FEh –0.07 dB FFh 0 dB (default) PROGRAM REGISTER 1 res: Bits 15:11 – Reserved These bits are reserved and should be set to 0.
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PCM3000 PCM3001 SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 PDWN: www.ti.com Bit 8 – ADC Power-Down Control This bit places the ADC section in a power-down mode, forcing the output data to all zeroes. This has no effect on the DAC section or the contents of the mode registers. PDWN 0 Power-down mode disabled (default) 1 Power-down mode enabled BYPS: Bit 7 – ADC High-Pass Filter Bypass Control This bit enables or disables the high-pass filter for the ADC.
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PCM3000 PCM3001 www.ti.com MUT: SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 Bit 0 – DAC Soft Mute Control When set to 1, both left- and right-channel DAC outputs are muted at the same time. This muting is done by attenuating the data in the digital filter, so that there is no audible click noise when soft mute is turned on. MUT 0 Mute disabled (default) 1 Mute enabled PROGRAM REGISTER 3 res: Bits 15:11 – Reserved These bits are reserved and should be set to 0.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 THEORY OF OPERATION ADC SECTION The PCM3000/3001 ADC consists of a band-gap reference, a stereo single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. The block diagram in this data sheet illustrates the architecture of the ADC section.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 In 8 fS 18-Bit + + − + Z−1 + − + + Z−1 + + Z−1 + 5-Level Quantizer 4 3 Out 64 fS 2 1 0 B0008-02 Figure 32. 5-Level ∆Σ Modulator Block Diagram 0 −10 −20 −30 −40 Gain − dB −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 0 5 10 15 20 25 30 f − Frequency − kHz G027 Figure 33.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 APPLICATION INFORMATION APPLICATION AND LAYOUT CONSIDERATIONS TYPICAL CONNECTION A typical connection diagram for the PCM3000/3001 is shown in Figure 34. +5V 1 Register Control Interface 28 2 27 3 26 Reset Serial Control or Format Control (1) 2.2 µF(2) + 4.7 µF + 4.7 µF + 4 Line In Left-Channel 5 2.
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PCM3000 PCM3001 www.ti.com SBAS055A – OCTOBER 2000 – REVISED OCTOBER 2004 APPLICATION INFORMATION (continued) GROUNDING In order to optimize dynamic performance of the PCM3000/3001, the analog and digital grounds are not internally connected. PCM3000/3001 performance is optimized with a single ground plane for all returns. It is recommended to tie all PCM3000/3001 ground pins to the analog ground plane using low-impedance connections.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM3000E/2K SSOP DB 28 2000 330.0 17.4 8.5 10.8 2.4 12.0 16.0 Q1 PCM3001E/2K SSOP DB 28 2000 330.0 17.4 8.5 10.8 2.4 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM3000E/2K SSOP DB 28 2000 336.6 336.6 28.6 PCM3001E/2K SSOP DB 28 2000 336.6 336.6 28.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.