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FEATURES

APPLICATIONS

DESCRIPTION

Lch In

Rch In

Analog Front-End

Delta-Sigma

Modulator

Digital

Decimation

Filter

Serial Interface

and

Mode Control

Digital Out

Mode Control

System Clock

B0006-01

Digital In

Digital

Interpolation

Filter

Lch Out

Rch Out

Low-Pass Filter

and

Output Buffer

Multilevel

Delta-Sigma

Modulator

* PCM3002 Only

PCM3002

PCM3003

SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004

16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS

• Single 3-V Power Supply

• Monolithic 20-Bit ∆ Σ ADC and DAC

• Small Package: SSOP-24

• 16/20-Bit Input/Output Data

• Software Control: PCM3002

• DVC Applications

• Hardware Control: PCM3003

• DSC Applications

• Stereo ADC:

• Portable/Mobile Audio Applications

– Single-Ended Voltage Input

– Antialiasing Filter

– 64 × Oversampling

The PCM3002 and PCM3003 are low-cost,

– High Performance

single-chip stereo audio codecs (analog-to-digital and

digital-to-analog converters) with single-ended analog

• THD+N: –86 dB

voltage input and output.

• SNR: 90 dB

The ADCs and DACs employ delta-sigma modulation

• Dynamic Range: 90 dB

with 64-times oversampling. The ADCs include a

• Stereo DAC:

digital decimation filter, and the DACs include an

– Single-Ended Voltage Output

8-times oversampling digital interpolation filter. The

DACs also include digital attenuation, de-emphasis,

– Analog Low-Pass Filter

infinite zero detection, and soft mute to form a

– 64 × Oversampling

complete subsystem. The PCM3002 and PCM3003

– High Performance

operate with left-justified (ADC) and right-justified

(DAC) formats, while the PCM3002 also supports

• THD+N: –86 dB

other formats, including the I

S data format.

• SNR: 94 dB

The PCM3002 and PCM3003 provide a power-down

• Dynamic Range: 94 dB

mode that operates on the ADCs and DACs indepen-

• Special Features (PCM3002, PCM3003)

dently.

– Digital De-Emphasis: 32 kHz, 44.1 kHz,

The PCM3002 and PCM3003 are fabricated using a

48 kHz

highly advanced CMOS process, and are available in

– Power Down: ADC/DAC Independent

a 24-pin SSOP package. The PCM3002 and

• Special Features (PCM3002)

PCM3003 are suitable for a wide variety of

cost-sensitive consumer applications where good per-

– Digital Attenuation (256 Steps)

formance is required.

– Soft Mute

The PCM3002 programmable functions are controlled

– Digital Loopback

by software. The PCM3003 functions, which are

– Four Alternative Audio Data Formats

controlled by hardware, include de-emphasis,

• Sampling Rate: 4 kHz to 48 kHz

power-down, and audio data format selections.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (41 pages)

PAGE 1
PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 16/20-BIT SINGLE-ENDED ANALOG INPUT/OUTPUT STEREO AUDIO CODECS FEATURES • • • • • • • • • Monolithic 20-Bit ∆Σ ADC and DAC 16/20-Bit Input/Output Data Software Control: PCM3002 Hardware Control: PCM3003 Stereo ADC: – Single-Ended Voltage Input – Antialiasing Filter – 64× Oversampling – High Performance • THD+N: –86 dB • SNR: 90 dB • Dynamic Range: 90 dB Stereo DAC: – Single-Ended Voltage Output – Analo
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted PARAMETER CONDITIONS PCM3002E/3003E MIN TYP MAX UNITS 0.454 fS Hz Digital Filter Performance Pass band Stop band 0.583 fS Hz ±0.05 Pass-band ripple Stop-band attenuation –65 Delay time dB dB 17.4/fS s 0.019 fS mHz Voltage range 0.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VDD = VCC = 3 V, fS = 44.1 kHz, SYSCLK = 384 fS, and 16-bit data, unless otherwise noted PARAMETER CONDITIONS PCM3002E/3003E MIN TYP MAX UNITS –25°C to 85°C 2.7 3 3.6 VDC 0° C to 70°C (10) 2.4 3 3.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range MIN NOM MAX Analog supply voltage, VCC1, VCC2 2.7 3 3.6 Digital supply voltage, VDD 2.7 3 3.6 Analog input voltage, full scale (–0 dB) VCC = 3 V 1.8 Digital input logic family V V Vp-p CMOS System clock Digital input clock frequency 8.192 24.
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PCM3002 PCM3003 www.ti.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted ADC SECTION 4 0.006 3 −0.5 dB 0.004 0 25 50 75 THD+N − Total Harm. Dist. + Noise at −0.5 dB − % 90 SNR 86 −25 88 0 25 50 75 TA − Free-Air Temperature − °C G002 Figure 1. Figure 2. THD+N vs SUPPLY VOLTAGE DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE 5 −60 dB 0.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted −60 dB 4 0.008 0.006 3 0.004 2 −0.5 dB 0.002 44.1 94 92 92 Dynamic Range 90 90 SNR 88 88 86 1 32 94 86 32 48 44.1 48 fS − Sampling Frequency − kHz fS − Sampling Frequency − kHz SNR − Signal-to-Noise Ratio − dB 5 Dynamic Range − dB 0.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted 4 −60 dB 0.008 3 0.006 2 FS 0.004 1 0.002 2.1 2.4 2.7 3.0 3.3 3.6 98 98 96 96 Dynamic Range 94 94 SNR 92 92 90 2.1 0 3.9 2.4 2.7 3.0 3.3 3.6 90 3.9 VCC − Supply Voltage − V VCC − Supply Voltage − V G010 G009 Figure 9.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted OUTPUT SPECTRUM ADCs OUTPUT SPECTRUM (–60 dB, N = 8192) 0 −20 −20 −40 −40 Amplitude − dB Amplitude − dB OUTPUT SPECTRUM (–0.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, and fSIGNAL = 1 kHz, unless otherwise noted DACs OUTPUT SPECTRUM (–60 dB, N = 8192) −20 −20 −40 −40 Amplitude − dB 0 −60 −80 −60 −80 −100 −100 −120 −120 −140 −140 0 5 10 15 20 25 0 5 f − Frequency − kHz 10 15 20 25 f − Frequency − kHz G014 G016 Figure 16. Figure 17.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, fSYSCLK = 384 fS, DIN = BPZ, and VIN = BPZ, unless otherwise noted SUPPLY CURRENT ICC + IDD vs SUPPLY VOLTAGE ICC + IDD vs TEMPERATURE 25 2.0 ICC + IDD − mA ADC and DAC 15 1.5 ADC 10 1.0 DAC 5 0.5 2.5 20 ICC + IDD − mA 20 ICC + IDD: Power Down and Off − mA 2.5 15 1.5 ADC 10 1.0 DAC 5 0.5 Power Down and Off 0 2.1 2.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DECIMATION FILTER OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS 0 0 −20 Amplitude − dB Amplitude − dB −50 −100 −40 −60 −150 −80 −200 0 8 16 24 Normalized Frequency [× fS Hz] −100 0.0 32 0.2 0.4 0.6 0.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted HIGH-PASS FILTER HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE 0 0.2 −10 0.0 −20 Amplitude − dB Amplitude − dB −30 −40 −50 −60 −70 −80 −0.2 −0.4 −0.6 −0.8 −90 −100 0.0 −1.0 0.1 0.2 0.3 0.4 Normalized Frequency [× fS/1000 Hz] 0.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DIGITAL FILTER PASS-BAND RIPPLE CHARACTERISTICS (fS = 44.1 kHz) 0 0.00 −20 −0.20 −40 −0.40 Level − dB Level − dB OVERALL FREQUENCY CHARACTERISTICS (fS = 44.1 kHz) −60 −80 −0.60 −0.80 −100 −1.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted DE-EMPHASIS ERROR (44.1 kHz) 0.6 −2 0.4 −4 0.2 Error − dB Level − dB DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) 0 −6 0.0 −8 −0.2 −10 −0.4 −12 −0.6 0 5k 10k 15k 20k 25k 0 4999.8375 f − Frequency − Hz 9999.675 14999.
PAGE 17
PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued) All specifications at TA = 25°C, VCC = VDD = 3 V, fS = 44.1 kHz, and fSYSCLK = 384 fS, unless otherwise noted ANALOG LOW-PASS FILTER INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1 Hz–100 kHz) 20 0.15 0 0.10 −20 0.05 Level − dB Level − dB INTERNAL ANALOG FILTER FREQUENCY RESPONSE (1 Hz–10 MHz) −40 0.00 −60 −0.05 −80 −0.10 −100 −0.
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PCM3002 PCM3003 www.ti.
PAGE 19
PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 1.0 µF + 3 VINR 30 kΩ − − (+) + + (−) 21 4.7 µF VCOM Delta-Sigma Modulator + 4 4.7 µF VREF1 + 5 4.7 µF VREF2 + VREF S0011-03 Figure 40. Analog Front-End (Single-Channel) PCM AUDIO INTERFACE The four-wire digital audio interface for the PCM3002/3003 comprises LRCIN (pin 10), BCKIN (pin 11), DIN (pin 15), and DOUT (pin 12).
PAGE 20
PCM3002 PCM3003 www.ti.
PAGE 21
PCM3002 PCM3003 www.ti.
PAGE 22
PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 t(LRP) 0.5 VDD LRCIN t(BCL) t(BCH) t(LB) t(BL) 0.5 VDD BCKIN t(BCY) t(DIH) t(DIS) 0.5 VDD DIN t(BDO) t(LDO) 0.
PAGE 23
PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 t(SCKH) H 0.7 VDD SYSCLK 0.3 VDD L 1/256 fS, 1/384 fS, or 1/512 fS t(SCKL) T0005-05 Figure 44. System Clock Timing System clock pulse duration, HIGH t(SCKH) 12 ns (min) System clock pulse duration, LOW t(SCKL) 12 ns (min) POWER-ON RESET Both the PCM3002 and PCM3003 have internal power-on reset circuitry. Power-on reset occurs when the system clock (SYSCLK) is active and VDD > 2.2 V.
PAGE 24
PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 Reset Removal or Power Down Off Internal Reset or Power Down Reset Ready/Operation Power Down t(DACDLY1) (16384/fS) DAC VOUT GND VCOM (0.5 VCC) t(ADCDLY1) (18432/fS) ADC DOUT Zero Data Zero Data Normal Data(1) T0019-02 (1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appears initially. Figure 46.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 Synchronization Lost State of Synchronization Synchronous Resynchronization Asynchronous Synchronous t(DACDLY2) (32/fS) Within 1/fS DAC VOUT Undefined Data Normal Data VCOM Normal Data (0.5 VCC) t(ADCDLY2) (32/fS) ADC DOUT Undefined Data Normal Data Normal Data(1) Zero Data T0020-03 (1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant) appears initially.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 ML MC MD B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 T0023-01 Figure 49. Control Data Input Format t(MHH) t(MLH) t(MLS) 0.5 VDD ML t(MCL) t(MLL) t(MCH) MC 0.5 VDD t(MCY) LSB MD 0.
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PCM3002 PCM3003 www.ti.
PAGE 28
PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 A[1:0] www.ti.com Bits 10, 9: Register address These bits define the address for register 0: A1 A0 0 0 REGISTER Register 0 LDL Bit 8: DAC attenuation data load control for left channel This bit is used to set analog outputs of the left and right channels simultaneously. The output level is controlled by AL[7:0] attenuation data when this bit is set to 1.
PAGE 29
PCM3002 PCM3003 www.ti.com A[1:0] SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 Bits 10, 9: Register address These bits define the address for register 2: A1 A0 1 0 PDAD: PDAD REGISTER Register 2 Bit 8: ADC power-down control This bit places the ADC section in the lowest power-consumption mode. The ADC operation is stopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADC power-down mode enable.
PAGE 30
PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 DEM[1:0]: Bits 2, 1: DAC de-emphasis control These bits select the de-emphasis mode as shown below: DEM1 DEM0 0 0 De-emphasis 44. 1 kHz ON 0 1 De-emphasis OFF (default) 1 0 De-emphasis 48 kHz ON 1 1 De-emphasis 32 kHz ON MUT: DE-EMPHASIS STATUS Bit 0: DAC soft mute control When set to 1, both left- and right-channel DAC outputs are muted at the same time.
PAGE 31
PCM3002 PCM3003 www.ti.com res: SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 Bit 0: Reserved This bit is reserved and should be set to 0. PCM3003 DATA FORMAT CONTROL The PCM3003 has hardware functional control using PDAD (pin 7) and PDDA (pin 8) for power-down control; DEM0 (pin 18) and DEM1 (pin 17) for de-emphasis; and 20BIT (pin 16) for 16/20-bit format selection.
PAGE 32
PCM3002 PCM3003 SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 www.ti.com APPLICATION AND LAYOUT CONSIDERATIONS POWER-SUPPLY BYPASSING The digital and analog power supply lines to PCM3002/3003 should be bypassed to the corresponding ground pins with both 0.1-µF ceramic and 10-µF tantalum capacitors as close to the device pins as possible.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 +3 V Analog VCC 0.1 µF and 10 µF(1) + Rch In PCM3002/3003 1 µF(3) + 1 4.7 µF(2) + 4.7 µF(2) + µF(3) + Lch In VCC2 24 2 VCC1 AGND1 23 3 VINR AGND2 22 4 VREF1 VCOM 21 5 VREF2 VOUTR 20 6 VINL SYSCLK Audio Interface 1 VCC1 VOUTL 19 4.7 µF(2) + 4.7 µF(4) + 4.
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PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 THEORY OF OPERATION ADC SECTION The PCM3002/3003 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully differential fifth-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit.
PAGE 35
PCM3002 PCM3003 www.ti.com SBAS079A – OCTOBER 2000 – REVISED OCTOBER 2004 THEORY OF OPERATION (continued) In 8 fS 21-Bit + + + Z−1 − + − + + Z−1 + + Z−1 + 5-Level Quantizer 4 3 Out 64 fS 2 1 0 B0008-01 Figure 53. Five-Level Delta-Sigma Modulator Block Diagram 0 −10 −20 −30 −40 Gain − dB −50 −60 −70 −80 −90 −100 −110 −120 −130 −140 −150 0 5 10 15 20 25 30 f − Frequency − kHz G040 Figure 54.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 37
PACKAGE OPTION ADDENDUM www.ti.com 12-Jan-2007 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 38
PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM3002E/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1 PCM3002EG/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.0 Q1 PCM3003E/2K SSOP DB 24 2000 330.0 17.4 8.5 8.6 2.4 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 13-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM3002E/2K SSOP DB 24 2000 336.6 336.6 28.6 PCM3002EG/2K SSOP DB 24 2000 336.6 336.6 28.6 PCM3003E/2K SSOP DB 24 2000 336.6 336.6 28.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.