Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsPCM3052ARTF

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FEATURES

DESCRIPTION

PCM3052A

SLES160 – NOVEMBER 2005

24-BIT, 96-kHz STEREO AUDIO CODEC WITH

MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA

• Multiple Functions With I

C Interface:

• Microphone Amplifier and Bias

– Digital De-Emphasis: 32-, 44.1-, 48-kHz

– Monaural Microphone Amplifier: 34-dB Gain

– Zipper-Noise-Free Digital Attenuation and

at Differential Input

Soft Mute for DAC

– Microphone Bias: 1 mA at 3.75 V

– HPF Bypass Control for ADC

• Multiplexer and PGA

– S/PDIF Output Control

– Multiplex of Stereo Single-Ended Line

– Power Down: ADC/DAC Independently

Inputs and Monaural Microphone Amplifier

• External Power-Down Pin:

– 0.1 Vrms to 1.5 Vrms Full-Scale Input Range

– ADC/DAC Simultaneously

– 22-k Ω Input Resistance at 0.1-Vrms Input

• Audio Data Format: 24-Bit I

S Only

– 20 dB to –4 dB/range, 1 dB/step PGA

• Sampling Rate:

• Reference Output: ± 10 mA at 2.5 V

– 16–96 kHz for Both ADC and DAC

• 24-Bit Delta-Sigma ADC and DAC

• System Clock: 256 f

Only

• Stereo ADC:

• Dual Power Supplies:

– Full-Scale Input: 3 Vp-p

– 5 V for Analog and 3.3 V for Digital

– Antialiasing Filter Included

• Package: VQFN-32

– 1/64 Decimation Filter:

• Pass-Band Ripple: ± 0.05 dB

• Stop-Band Attenuation: –65 dB

The PCM3052A is a low-cost, single-chip, 24-bit

stereo audio codec (ADC and DAC) with

– On-Chip High-Pass Filter: 0.91 Hz at

single-ended analog voltage input and output. It also

= 48 kHz

has an analog front end consisting of a 34-dB

– High Performance:

microphone amplifier, microphone bias generator, 2

• THD+N: –94 dB (Typical)

stereo multiplexers, and a wide-range PGA. Analog-

to-digital converters (ADCs) employ delta-sigma

• SNR: 101 dB (Typical)

modulation with 64-times oversampling. On the other

• Dynamic Range: 101 dB (Typical)

hand, digital-to-analog converters (DACs) employ

• Stereo DAC:

modulation with 64- and 128-times oversampling.

ADCs include a digital decimation filter with a

– Single-Ended Voltage Output: 4 Vp-p

high-pass filter, and DACs include an 8-times

– Analog Low-Pass Filter Included

oversampling digital interpolation filter. The

– × 8 Oversampling Digital Filter:

PCM3052A has many functions which are controlled

• Pass-Band Ripple: ± 0.03 dB

using the I

C interface: DAC digital de-emphasis,

digital attenuation, soft mute etc. The PCM3052A

• Stop-Band Attenuation: –50 dB

also has an S/PDIF output pin for the DAC digital

– High Performance:

input. The power-down mode, which works on ADCs

• THD+N: –97 dB (Typical)

and DACs simultaneously, is provided by an external

pin. The PCM3052A is suitable for a wide variety of

• SNR: 105 dB (Typical)

cost-sensitive PC audio (recorder and player)

• Dynamic Range: 104 dB (Typical)

applications where good performance is required.

• S/PDIF Output for DAC Digital Input

The PCM3052A is fabricated using a highly advanced

CMOS process and is available in a small 32-pin

VQFN package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

System Two, Audio Precision are trademarks of Audio Precision, Inc.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (47 pages)

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PCM3052A SLES160 – NOVEMBER 2005 24-BIT, 96-kHz STEREO AUDIO CODEC WITH MICROPHONE AMPLIFIER, BIAS, MUXTIPLEXER, AND PGA FEATURES • • • • • • • Microphone Amplifier and Bias – Monaural Microphone Amplifier: 34-dB Gain at Differential Input – Microphone Bias: 1 mA at 3.75 V Multiplexer and PGA – Multiplex of Stereo Single-Ended Line Inputs and Monaural Microphone Amplifier – 0.1 Vrms to 1.5 Vrms Full-Scale Input Range – 22-kΩ Input Resistance at 0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.5 Vrms AFE MULTIPLEXER Input channel 2 CH Input range for full scale VINL, VINR 0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DEVICE INFORMATION (continued) PIN ASSIGNMENTS VOUTL VOUTR VCC2 AGND2 I2CEN ADR SCL SDA SCKI 25 24 23 22 21 20 19 18 17 RTF PACKAGE (TOP VIEW) 12 DIN VCC3 31 11 BCK REFO 32 10 LRCK 9 30 PDWN AGND3 AGND1 DOUT 8 13 7 29 VCC1 MINP 6 DOUTS VINR 14 5 28 VREF2 MINM 4 DGND VREF1 15 3 27 L/M MBIAS 2 VDD VINL 16 1 26 ATEST VCOM P0036-01 TERMINAL FUNCTIONS TERMINAL NAME ADR NO.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL NAME I/O NO. DESCRIPTION SCKI 17 I System clock input, 256 fS (3) SCL 19 I Mode control clock input SDA 18 I/O VCC1 7 ADC analog power supply, 5 V VCC2 23 DAC analog power supply, 5 V VCC3 31 Microphone amplifier and bias analog power supply, 5 V VCOM 26 DAC common voltage decoupling, 0.5 VCC2 VDD 16 Digital power supply, 3.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS 0.2 0 −1 −2 −3 −0.2 Amplitude − dB Amplitude − dB 0.0 −0.4 −0.6 −4 −4.13 dB at 0.5 fS −5 −6 −7 −8 −0.8 −9 −1.0 0.0 0.1 0.2 0.3 0.4 Normalized Frequency [×fS] −10 0.45 0.5 0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. ANALOG FILTER (Line Input, PGA Gain = 0 dB) ANTIALIASING FILTER STOP-BAND CHARACTERISTICS ANTIALIASING FILTER PASS-BAND CHARACTERISTICS 0 0.0 −10 −0.2 Amplitude − dB Amplitude − dB f−3dB = 300 kHz −20 −30 −40 −0.4 −0.6 −0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. DIGITAL FILTER FREQUENCY RESPONSE, STOP BAND (Sharp Rolloff) FREQUENCY RESPONSE, PASS BAND (Sharp Rolloff) 0.2 0 −20 0.0 Amplitude − dB Amplitude − dB −40 −60 −80 −0.2 −0.4 −0.6 −100 −0.8 −120 −140 0 1 2 3 −1.0 0.0 4 Frequency [×fS] 0.1 0.2 0.4 0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. DE-EMPHASIS ERROR (fS = 44.1 kHz) 0.5 −1 0.4 −2 0.3 −3 0.2 −4 0.1 Error − dB Level − dB DE-EMPHASIS (fS = 44.1 kHz) 0 −5 −6 0.0 −0.1 −7 −0.2 −8 −0.3 −9 −0.4 −10 −0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256fS, 24-bit data, unless otherwise noted. ANALOG FILTER STOP-BAND CHARACTERISTICS (1 kHz–10 MHz) PASS-BAND CHARACTERISTICS (100 Hz–1 MHz) 0 0.0 −10 −0.2 Amplitude − dB Amplitude − dB f−3dB = 300 kHz −20 −30 −40 −0.4 −0.6 −0.8 −50 1 10 100 1k 10k f − Frequency − kHz −1.0 0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (ADC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. LINE INPUT (at PGA Gain = 0 dB) 110 Dynamic Range and SNR − dB −85 −90 −95 −100 −40 −15 10 35 60 TA − Free-Air Temperature − °C Dynamic Range 100 SNR 95 −40 85 −15 10 35 60 TA − Free-Air Temperature − °C G019 Figure 20.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (ADC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY 110 −85 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise at −0.5 dB − dB THD+N vs SAMPLING FREQUENCY −90 −95 −100 32 105 Dynamic Range SNR 100 95 48 64 80 fS − Sampling Frequency − kHz Figure 23.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (DAC SECTION) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. −90 Dynamic Range and SNR − dB 110 −95 −100 −105 −40 −15 10 35 60 TA − Free-Air Temperature − °C 105 Dynamic Range 100 95 −40 85 −15 10 35 60 TA − Free-Air Temperature − °C G025 Figure 26.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (DAC SECTION) (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. DYNAMIC RANGE AND SNR vs SAMPLING FREQUENCY −90 110 Dynamic Range and SNR − dB THD+N − Total Harmonic Distortion + Noise at 0 dB − dB THD+N vs SAMPLING FREQUENCY −95 −100 −105 32 SNR 105 Dynamic Range 100 95 48 64 80 fS − Sampling Frequency − kHz Figure 29.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. ADC OUTPUT SPECTRUM (Line Input, at PGA Gain = 0 dB) OUTPUT SPECTRUM (–60 dB, N = 8192) 0 0 −20 −20 −40 −40 Amplitude − dB Amplitude − dB OUTPUT SPECTRUM (–0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VCC1 = VCC2 = VCC3 = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI = 256 fS, 24-bit data, unless otherwise noted. SUPPLY CURRENT SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SAMPLING FREQUENCY, ADC AND DAC OPERATING 45 45 40 30 25 20 15 IDD 10 25 20 0 −15 10 35 60 85 32 G035 64 80 Figure 35. Figure 36.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION ADC SECTION The ADC block consists of a reference circuit, two channels of single-ended to differential converter, a fifth-order delta-sigma modulator with fully differential architecture, a decimation filter with high-pass filter, and a serial interface circuit which is also used as the serial interface for the DAC input signal as shown in the block diagram.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION (continued) − + IN 8 fS + + + Z–1 − + + + Z–1 + + + + + Z–1 Z–1 + 8-Level Quantizer OUT 64 fS B0008-03 Figure 40. 8-Level Delta-Sigma Modulator Block Diagram 0 125 −20 120 Dynamic Range − dB Amplitude − dB −40 −60 −80 −100 −120 115 110 105 100 −140 95 −160 −180 90 0 1 2 3 4 5 6 7 fS − Sampling Frequency − kHz Figure 41.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 THEORY OF OPERATION (continued) SYSTEM CLOCK The system clock for the PCM3052A must be 256 fS, where fS is the audio sampling rate, 16 kHz to 96 kHz. Table 1 lists typical system clock frequencies, and Figure 43 illustrates the system clock timing. Table 1. Typical System Clock SAMPLING RATE FREQUENCY (fS) – LRCK SYSTEM CLOCK FREQUENCY – MHz 16 kHz 4.096 256 fS 32 kHz 8.192 44.1 kHz 11.2896 48 kHz 12.288 96 kHz 24.576 tw(SCKH) 2V System Clock 0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DOUTS is driven LOW immediately after PDWN is asserted and recovers about 40/fS following PDWN release. Notes: 1. Large pop noises can be generated on VOUTL and VOUTR if the power supply is turned off during normal operation. 2. To switch PDWN during fade-in or fade-out causes an immediate change between fade-in and fade-out. 3. Changing mode controls during normal operation can degrade analog performance.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 VCC1, VCC2, VCC3, VDD LRCK, BCK, SCKI (VCC1 − VCC3 = 5 V, VDD = 3.3 V Typ) 0V Synchronous Clocks Synchronous Clocks PDWN 1024 SCKI Internal Reset Normal Operation Power Down t(DACDLY1), 2100 /fS VOUTL, VOUTR Normal Operation t(DACDLY1), 2100 /fS VCOM (0.5 VCC2) 0.5 VCC2 t(ADCDLY1), 4500 /fS ZERO DOUT About 40/fS DOUTS LOW T0098-01 Figure 45.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 PCM AUDIO INTERFACE Digital audio data is interfaced to the PCM3052A on LRCK (pin 10), BCK (pin 11), DIN (pin 12), DOUT (pin 13), and DOUTS (pin 14). The PCM3052A can accept 24-bit I2S format only. In case of AC-3 type output data for DOUTS, bits 17 to 24 of DIN must be held LOW. See the Digital Audio Interface Transmitter (DIT) section of this data sheet. Table 2.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 t(LRP) 1.4 V LRCK t(BCL) t(LB) t(BCH) t(BL) 1.4 V BCK t(BCY) t(DIS) t(DIH) 1.4 V DIN t(BDO) t(LDO) 0.5 VDD DOUT T0021−03 PARAMETER tBCY BCK pulse cycle time tBCH MIN MAX UNIT 160 ns BCK pulse duration, HIGH 70 ns tBCL BCK pulse duration, LOW 70 ns tBL BCK rising edge to LRCK edge 20 ns tLB LRCK edge to BCK rising edge 20 ns tLRP LRCK pulse duration 4.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM The PCM3052A operates with LRCK and BCK synchronized to the system clock in slave mode. The PCM3052A does not need specific phase relationship among LRCK, BCK, and the system clock, but does require the synchronization of LRCK, BCK, and the system clock. If the relationship between system clock and LRCK changes more than ±6 BCKs during one sample period due to LRCK jitter, etc.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 REFERENCE OUTPUT The PCM3052A has a reference output pin (RFFO, pin 32) to supply reference voltage (0.5 VCC1) to external components. The pin has 10-mA sink/source capability with 6-Ω output impedance. −1 mA (0.75 VCC1) MBIAS 48 Ω + MINM − Electret Microphone MUX 34 dB + MINP REF (0.5 VCC1) REFO 6Ω + 10 mA S0124-01 Figure 49.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 MULTIPLEXER AND PGA The PCM3052A has built-in analog front-end circuit which is shown in Figure 50. Multiplexer input and PGA gain are selected by mode control via the serial port, as shown in the Serial Control Port for Mode Control section. The full-scale input voltage range is 0.1 Vrms to 1.5 Vrms, and it can be adjusted to an adequate level for following the ADC sections. VINL and VINR input resistance is maintained above 22 kΩ for all PGA gains.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Each bit after the audio sample word is assigned in the PCM3052A as follows.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SERIAL CONTROL PORT FOR MODE CONTROL The several built-in functions of the PCM3052A can be controlled through the I2C format serial-control port, SDA (pin 18) and SCL (pin 19). The PCM3052A supports the I2C serial bus and the data transmission protocol for standard mode as a slave device. This protocol is explained in I2C specification 2.0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Write Operation The PCM3052A supports receiver function. A master can write to any PCM3052A registers using single or multiple accesses. The master sends a PCM3052A slave address with a write bit, a register address, and the data. If multiple access is required, the address is that of the starting register, followed by the data to be transferred. When the data are received properly, the index register is incremented by 1 automatically.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TIMING DIAGRAM Start Repeated Start Stop t(D-HD) t(BUF) t(D-SU) t(SDA-R) t(SDA-F) t(P-SU) SDA t(SCL-R) t(RS-HD) t(LOW) SCL t(S-HD) t(HI) t(RS-SU) t(SCL-F) T0050-01 PARAMETER CONDITIONS MIN MAX UNIT 100 kHz f(SCL) SCL clock frequency Standard mode t(BUF) Bus free time between STOP and START condition Standard mode 4.7 µs t(LOW) Low period of the SCL clock Standard mode 4.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 Table 4. User-Programmable Mode Controls FUNCTION RESET DEFAULT REGISTER BIT(S) 0 dB, no attenuation 65 and 66 AT1[7:0], AT2[7:0] Mode control register reset (ADC and DAC) Normal operation 67 MRST System reset (ADC and DAC) Normal operation 67 SRST ADC power-save control (ADC) Normal operation 67 ADPSV DAC Power Save Control (DAC) Normal operation 67 DAPSV Mute disabled 68 MUT[2:1] OVR1 Digital attenuation control, 0 dB to –63 dB in 0.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 REGISTER DEFINITIONS B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 REGISTER 65 0 1 0 0 0 0 0 1 AT17 AT16 AT15 AT14 AT13 AT12 AT11 AT10 REGISTER 66 0 1 0 0 0 0 1 0 AT27 AT26 AT25 AT24 AT23 AT22 AT21 AT20 ATx[7:0]: Digital Attenuation Level Setting (DAC) Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 SRST = 0 Re-synchronization SRST = 1 Normal operation (default) The SRST bit controls system reset. The PCM3052A does not go into power-down state. The mode control register is not reset by this control. Also pop-noise may be generated. ADPSV: ADC Power-Save Control (ADC) Default value: 0 ADPSV = 0 Normal operation (default) ADPSV = 1 Power-save mode The ADPSV bit controls ADC power-save mode.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 1 0 1 RSV DMF1 DMF0 DM12 RSV RSV RSV RSV REGISTER 69 DMF[1:0]: Sampling Frequency Selection for the De-Emphasis Function (DAC) Default value: 01 DMF[1:0] DE-EMPHASIS SAMPLING RATE SELECTION 00 44.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 1 0 0 0 RSV RSV AML PG4 PG3 PG2 PG1 PG0 REGISTER 72 AML: Multiplexer Input Channel Selection (ADC) Default value: 0 AML MULTIPLEXER INPUT CHANNEL SELECTION 0 Line (default) 1 Microphone The AML bit selects the input channel of multiplexer.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 0 1 0 0 1 1 0 1 DACMSK RSV AFI5 AFI4 AFI3 REGISTER 77 B2 B1 COPY AUDIO B0 DITMSK DACMSK: DAC Output Control (DAC) Default value: 0 DACMSK = 0 Mask disable (default) DACMSK = 1 Mask DIN to BPZ level The DACMSK bit is used to mask DIN to BPZ level. The analog outputs from DAC is forced to BPZ level immediately. Larger noise may be generated by this control.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 1 1 1 0 CAT15 CAT14 CAT13 CAT12 CAT11 CAT10 CAT9 CAT8 REGISTER 78 CAT[15:8]: Category Code (DIT) Default value: 0000 0000 (general) The CAT[15:8] bits control bits[15:8] of channel status bits in compliance with IEC958.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 TYPICAL CIRCUIT CONNECTION Figure 56 illustrates typical circuit connection. Line Out GND Control 5V 3.
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PCM3052A www.ti.com SLES160 – NOVEMBER 2005 DESIGN AND LAYOUT CONSIDERATIONS IN APPLICATION Power Supply Pins (VCC1, VCC2, VCC3, VDD) The digital and analog power supply lines to the PCM3052A should be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC and DAC.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM3052ARTFR Package Package Pins Type Drawing VQFN RTF 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 13.4 Pack Materials-Page 1 5.5 B0 (mm) K0 (mm) P1 (mm) 6.5 1.55 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM3052ARTFR VQFN RTF 32 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.