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FEATURES

APPLICATIONS

DESCRIPTION

PCM3060

SLAS533B – MARCH 2007 – REVISED MARCH 2008

24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC

and DAC

• 24-Bit Delta-Sigma ADC and DAC – Digital De-Emphasis: 32, 44.1, 48 kHz for

DAC

• ADC, DAC Asynchronous Operation

– Power Down: ADC/DAC Independently

• Stereo ADC:

– Asynchronous/Synchronous Control for

– High Performance: (Typical, 48 kHz)

ADC/DAC Operation

– THD+N: – 93 dB

• External Reset and Power-Down Pin:

– SNR: 99 dB

– ADC/DAC Simultaneously

– Dynamic Range: 99 dB

• Audio Interface Mode:

– Sampling Rate: 16 – 96 kHz

– ADC/DAC Independent Master/Slave

– System Clock: 256, 384, 512, 768 f

• Audio Data Format:

– Full Scale Input: 3 Vp-p

– ADC/DAC Independent

– Antialiasing Filter Included

– I

S, Left-Justified, Right-Justified

– 1/64 Decimation Filter:

• Dual Power Supplies:

– Pass-Band Ripple: ± 0.05 dB

– 5-V for Analog and 3.3-V for Digital

– Stop-Band Attenuation: – 65 dB

• Package: TSSOP-28

– On-Chip High-Pass Filter: 0.91 Hz at

= 48 kHz

• Stereo DAC:

• DVD-RW

– High Performance: (Typical, Differential,

• Digital TV

48 kHz)

• Digital Set-Top Box

– THD+N: – 94 dB

• Audio-Visual Applications

– SNR: 105 dB

– Dynamic Range: 104 dB

– Sampling Rate: 16 – 192 kHz

The PCM3060 is a low-cost, high-performance,

single-chip, 24-bit stereo audio codec with

– System Clock: 128, 192, 256, 384,

single-ended analog inputs and differential analog

512, 768 f

outputs.

– Differential Voltage Output: 8 Vp-p

The stereo 24-bit ADC employs a 64-times

– Single-Ended Voltage Output: 4 Vp-p

delta-sigma modulator. It supports 16 – 96 kHz

– Analog Low-Pass Filter Included

sampling rates and a 16/24-bit digital audio output

– 4 × /8 × Oversampling Digital Filter:

word on the audio interface.

– Pass-Band Ripple: ± 0.04 dB

The stereo 24-bit DAC employs a 64- or 128-times

– Stop-Band Attenuation: – 50 dB

delta-sigma modulator. It supports 16 – 192 kHz

sampling rates and a 16/24-bit digital audio input

– Zero Flags

word on the audio interface.

• Flexible Mode Control

The PCM3060 supports fully independent operation

– 3-Wire SPI, 2-Wire I

C Compatible Serial

of the sampling rate and audio interface for the ADC

Control Interface

and DAC.

– Hardware Control Mode

Each audio interface supports I

S, left-justified, and

• Multiple Functions via SPI or I

C Interface:

right-justified formats with 16/24-bit words.

– Digital Attenuation and Soft Mute for ADC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (48 pages)

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PCM3060 SLAS533B – MARCH 2007 – REVISED MARCH 2008 24-BIT, 96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC FEATURES 1 • • • • • • 24-Bit Delta-Sigma ADC and DAC ADC, DAC Asynchronous Operation Stereo ADC: – High Performance: (Typical, 48 kHz) – THD+N: –93 dB – SNR: 99 dB – Dynamic Range: 99 dB – Sampling Rate: 16–96 kHz – System Clock: 256, 384, 512, 768 fS – Full Scale Input: 3 Vp-p – Antialiasing Filter Included – 1/64 Decimation Filter: – Pass-Band Ripple: ±0.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data (unless otherwise noted).
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data (unless otherwise noted).
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data (unless otherwise noted).
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data (unless otherwise noted). PARAMETER TEST CONDITIONS DIGITAL FILTER PERFORMANCE PCM3060PW MIN TYP MAX UNIT SLOW ROLLOFF 0.308 fS Pass band Stop band 0.73 fS Pass-band ripple < 0.308 fS Stop-band attenuation > 0.73 fS Hz Hz ±0.
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PCM3060 www.ti.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 Table 1.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 BLOCK DIAGRAM VINL SE to Diff. Converter Delta-Sigma Modulator VDD Decimation Filter with HPF VINR SE to Diff.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 TYPICAL PERFORMANCE CURVES OF ADC INTERNAL FILTER All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data, unless otherwise noted. DIGITAL FILTER DECIMATION FILTER, STOP-BAND CHARACTERISTICS DECIMATION FILTER, PASS-BAND CHARACTERISTICS 0.1 0 −20 0.0 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −0.1 −0.2 −0.3 −120 −0.4 −140 −160 0 8 16 24 −0.5 0.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 TYPICAL PERFORMANCE CURVES OF DAC INTERNAL FILTER All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data, unless otherwise noted. DIGITAL FILTER INTERPOLATION FILTER, STOP BAND (SHARP-ROLL OFF) INTERPOLATION FILTER, PASS BAND (SHARP-ROLL OFF) 0.1 0 −20 0.0 Amplitude − dB Amplitude − dB −40 −60 −80 −100 −0.1 −0.2 −0.3 −120 −0.4 −140 −160 0 1 2 3 −0.5 0.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 TYPICAL ADC PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data, unless otherwise noted. −88 104 VIN = –0.5 dB −90 102 −92 −94 −96 −98 −100 −25 Dynamic Range 100 98 SNR 96 94 0 25 50 75 TA − Free-Air Temperature − °C 92 −25 100 G009 25 50 75 100 G010 Figure 9. Figure 10.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 TYPICAL DAC PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data, unless otherwise noted.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, fS = 48 kHz, SCKI1 = SCKI2 = 512 fS, 24-bit data, unless otherwise noted.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 DEVICE DESCRIPTION ASYNCHRONOUS OPERATION The PCM3060 supports complete asynchronous operation between the ADC and DAC by receiving two independent system clocks on SCKI1 and SCKI2. Also, the PCM3060 supports synchronous operation between ADC and DAC by receiving one common system clock on either SCKI1 or SCKI2 and controlling the system clock configuration through register 67 or 72 in serial mode control.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 POWER-ON RESET AND EXTERNAL RESET SEQUENCE The PCM3060 has both an internal power-on reset circuit and an external reset circuit. The sequences for both resets are shown in the following. Figure 22 illustrates the timing of the internal power-on reset. Initialization (reset) is done automatically at the time when VDD exceeds 2.2 V typical.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 POWER-ON RESET AND EXTERNAL RESET SEQUENCE (Continued) VDD (VDD = 3.3 V typ.) (VDD = 2.7 V min.) (VDD = 2.2 V typ.) 0V SCKIx, BCKx, LRCKx Synchronous Clocks MODE RST ADPSV DAPSV (1) 1024 SCKIx 1024 SCKIx Internal Reset Normal Operation Power Down t(DACDLY1) 2048/fS VOUTL+/– VOUTR+/– t(DACDLY2) 1616/fS 0.5 VCC VCOM (0.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 (VDD = 3.3 V typ.) VDD SCKIx, BCKx, LRCKx 0V Synchronous Clocks Synchronous Clocks MODE tRST 2048/fS min. RST 2048/fS min. ADPSV DAPSV (1) 1024 SCKIx Internal Reset Normal Operation t(DACDLY2) 1616/fS Normal Operation Power Down t(DACDLY1) 2048/fS VOUTL+/– VOUTR+/– t(DACDLY2) 1616/fS 0.5 VCC VCOM (0.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 PCM AUDIO INTERFACE Audio Interface Mode and Timing The digital audio data can be interfaced in either slave or master mode, and this interface mode is selectable using the serial mode control described in the Mode Control section. The interface mode is also selectable independently for the ADC and the DAC. DIN is always input to the PCM3060 and DOUT is always an output from the PCM3060.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 SCKI1/2 (Input) 1.4 V t(BCH) t(BCL) t(BCD) t(BCD) BCK1/2 (Output) 0.5 VDD t(BCY) t(LRD) LRCK1/2 (Output) 0.5 VDD t(DOD) 0.5 VDD DOUT t(DIS) t(DIH) DIN 1.4 V T0248-01 SYMBOL PARAMETERS MIN TYP MAX 0.4 t(BCY) 0.5 t(BCY) 0.6 t(BCY) 0.4 t(BCY) 0.5 t(BCY) 0.
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PCM3060 www.ti.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM As the PCM3060 operates under the system clock (SCKI1/2) and the audio sampling clock (LRCK1/2), SCKI1/2 and LRCK1/2 must have a specific relationship in slave mode. The PCM3060 does not need a specific phase relationship between audio the interface clocks (LRCK1/2, BCK1/2) and system clock (SCKI1/2), but does require a frequency synchronization of LRCK1/2, BCK1/2, and SCKI1/2.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 ANALOG INPUTS TO ADC The PCM3060 has two independent input channels, VINL and VINR. These are single-ended (unbalanced) inputs, each capable of 0.6-VCC Vpp input with 10-kΩ input resistance, typically. ANALOG OUTPUTS FROM DAC The PCM3060 has two independent output channels, VOUTL and VOUTR. These are differential, (balanced) outputs, each capable of driving 0.8-VCC Vpp (1.6-Vpp in differential) typical with a 10-kΩ dc-coupled load.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 MODE CONTROL The PCM3060 supports the following three types of mode control interface and four types of operation configuration, according to the input state of MODE (pin 28) as follows. The pullup or pulldown resistor must be 220 kΩ ±5%.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 Register Write Operation All single-write operations via the serial control port use 16-bit data words. Figure 28 shows the control data word format. The most significant bit must be a 0. There are seven bits, labeled IDX[6:0], that set the register index (address) for the write operation. The least significant eight bits, D[7:0], contain the data to be written to the register specified by IDX[6:0].
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 Timing Requirements Figure 30 shows a detailed timing diagram for the 3-wire serial control interface. These timing parameters are critical for proper control port operation. t(MHH) 1.4 V MS t(MSS) t(MCL) t(MSH) t(MCH) 1.4 V MC t(MCY) LSB 1.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 The PCM3060 has 7 bits for its own slave address. The first six bits (MSBs) of the slave address are factory preset to 10 0011. The next bit of the address byte is the device select bit, which can be user-defined by the ADR pin (pin 27). Two PCM3060s at maximum can be connected on the same bus at one time. Each PCM3060 responds when it receives its own slave address.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 Timing Diagram The detailed timing diagram for SCL and SDA is shown as follows. Repeated Start Start Stop t(SDA-F) t(P-SU) t(D-HD) t(D-SU) t(BUF) t(SDA-R) SDA t(SCL-R) t(S-HD) t(GW) t(LOW) SCL t(HI) t(S-HD) t(S-SU) t(SCL-F) T0050-04 Timing Characteristics SYMBOL STANDARD MODE PARAMETER MIN MAX FAST MODE MIN 100 MAX 400 UNIT f(SCL) SCL clock frequency t(BUF) Bus free time between STOP and START conditions 4.7 1.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 MODE CONTROL REGISTERS The PCM3060 has many user-programmable functions which are accessed via control registers, and they are programmed through the SPI or I2C serial control port. Table 3 lists the available mode control functions along with reset default conditions and associated register addresses. The register map is shown in Table 3. Table 3.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 REGISTER DEFINITIONS Register 64 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 0 0 0 MRST SRST ADPSV DAPSV RSV RSV RSV S/E MRST: Mode Control Register Reset (ADC and DAC) Default value: 1 MRST = 0 Set default value MRST = 1 Normal operation (default) The MRST bit controls reset of the mode control registers to their default values. Pop noise may be generated.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 DAPSV: DAC Power-Save Control (DAC) Default value: 1 DAPSV = 0 Normal operation DAPSV = 1 Power-save mode (default) The DAPSV bit controls DAC power-save mode. In power-save mode, DAC outputs are forced to Vcom with a fade-out sequence, the internal DAC data are reset and the DAC goes into the power-down state. For power-save mode release, a fade-in sequence is applied on the DAC outputs in resume process.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 1 0 0 0 1 0 1 FLT DMF1 DMF0 DMC RSV RSV ZREV AZRO Register 69 FLT: Digital Filter Rolloff Control (DAC) Default value: 0 FLT = 0 Sharp rolloff (Default) FLT = 1 Slow rolloff The FLT bit allows the user to select the digital filter roll-off that is best suited to their application. Sharp and Slow filter roll-off selections are available.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 Register 73 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 0 1 0 0 1 0 0 1 RSV RSV RSV ZCDD BYP B2 B1 DREV1 MUT12 B0 MUT11 ZCDD: Zero-Cross Detection Disable for Digital Attenuation (ADC) Default value: 0 ZCDD = 0 Zero-cross detection enabled (default) ZCDD = 1 Zero-cross detection disabled The ZCDD bit controls the zero-cross detect function for digital attenuation and mute.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 TYPICAL CIRCUIT CONNECTION Figure 33 illustrates typical circuit connection.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 Application Examples for Analog Input and Output a) Example of VCOM-biased buffering for 2-Vrms input with overvoltage protection. R2 Example of C, R values with gain (G) and corner frequency (fC) C2 C1 +V R1 R3 Input VINX –V VCOM C3 R1: 20 kW R2: 10 kW R3: 1 kW C1: 10 mF C2: 330 pF C3: 0.1 mF G: 0.5 fC: 48 kHz b) Example of capless differential to single-ended converter with LPF and gain for 2-Vrms standard output.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 DESIGN AND LAYOUT CONSIDERATIONS IN APPLICATION Power Supply Pins (VCC, VDD) The digital and analog power supply lines to the PCM3060 should be bypassed to the corresponding ground pins with 0.1-µF ceramic and 10-µF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC and DAC.
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PCM3060 www.ti.com SLAS533B – MARCH 2007 – REVISED MARCH 2008 Audio Interface Clocks In slave mode, PCM3060 does not require specific timing relationship between BCK1/LRCK1 and SCKI1, BCK2/LRCK2 and SCKI2, but there is a possibility of performance degradation with a certain timing relationship between them. In that case, specific timing-relationship control might solve this performance degradation.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.