Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 28

Audio Interface

Interpolation Filter

32-bit ∆Σ Modulator

Current

Segment

DAC

I/V

Analog

Mute

Zero Data

Detector

PLL

Clock

Charge

Pump

VCom

POR

Clock Halt

Detection

Advanced Mute Control

MCK

BCK

LRCK

CAPP

CAPM

VNEG

UVP/XSMT

LINE OUT

DOUT (I

through any

GPIO

PCM512x

Fixed-Function

Processing

(EQ, DRC)

MODE1

MS/MODE2

MOSI/SDA/ATT2

MC/SCL/ATT1

GPIO6/FLT

MISO/ADR1/FMT

GPIO

Power

Supply

CPVDD (3.3V)

AVDD (3.3V)

DVDD (1.8V or 3.3V)

GND

Program

RAM

Digital

Volume

Control

DIN (I

I/V

Current

Segment

DAC

Analog

Mute

SPI/I

GPIO5/ATT0

GPIO4/MAST

GPIO3/AGNS

GPIO2/ADR2/DOUT

UVP/

Reset

PCM5121, PCM5122

www.ti.com

SLAS763A –AUGUST 2012–REVISED SEPTEMBER 2012

RMS

DirectPath™, 112/106dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface

Check for Samples: PCM5121, PCM5122

FEATURES

Typical Performance (3.3V Power Supply)

• Register-Selectable Audio-Processing

Parameter PCM5122 PCM5121

Functions

SNR 112dB 106dB

– Dynamic Range Control (DRC)

Dynamic Range 112dB 106dB

– Equalization (EQ)

THD+N @ - 1dBFS –93dB –92dB

– Filtering

Full Scale Output 2.1V

RMS

(GND center)

• Market-Leading Low Out-of-Band Noise

Normal 8× Oversampling Digital Filter Latency: 20/f

• Selectable Digital-Filter Latency and

Low Latency 8× Oversampling Digital Filter Latency: 3.5/f

Performance

Sampling Frequency 8kHz to 384kHz

• No DC Blocking Capacitors Required

System Clock Multiples (f

SCK

): 64, 128, 192, 256, 384, 512,

768, 1024, 1152, 1536, 2048, 3072; up to 50 MHz

• Integrated Negative Charge Pump

• Internal Pop-Free Control For Sample-Rate

Changes Or Clock Halts

• Intelligent Muting System; Soft Up or Down

Ramp and Analog Mute For 120dB Mute SNR

With Popless Operation

Figure 1. PCM512x Functional Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2System Two Cascade, Audio Precision are trademarks of Audio Precision.

3DirectPath is a trademark of Texas, Instruments, Inc..

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (107 pages)

PAGE 1
PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 2VRMS DirectPath™, 112/106dB Audio Stereo DAC with 32-bit, 384kHz PCM Interface Check for Samples: PCM5121, PCM5122 FEATURES 1 Zero Data Detector 106dB Dynamic Range 112dB 106dB THD+N @ - 1dBFS –93dB –92dB Full Scale Output 2.1VRMS (GND center) Normal 8× Oversampling Digital Filter Latency: 20/fS Low Latency 8× Oversampling Digital Filter Latency: 3.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com space This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 spacer DEVICE INFORMATION PCM512x pin assignments-1 MODE1 tied DVDD : SPI mode GPIO2 16 GPIO3 15 13 GPIO5 14 GPIO4 MS 18 MODE1 17 11 MOSI 12 MC SCK 20 GPIO6 19 10 VCOM 8 AVDD 9 AGND DIN 22 BCK 21 7 OUTR MISO 24 LRCK 23 6 OUTL XSMT 25 5 VNEG LDOO 26 4 CAPM DVDD 28 3 CPGND 2 CAPP 1 CPVDD DGND 27 PCM512x (top view) Table 2.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 2. PCM512x SPI mode Terminal Functions (continued) TERMINAL 4 NAME PIN I/O DESCRIPTION LDOO 26 - Internal logic supply rail terminal for decoupling, 1.8V DGND 27 - Digital ground DVDD 28 - Digital power supply, 3.3V or 1.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 PCM512x pin assignments-2 MODE1 tied DGND and MODE2 tied DVDD : I2C mode ADR2 16 12 SCL GPIO3 15 MODE1 17 11 SDA 14 GPIO4 MODE2 18 10 VCOM 13 GPIO5 SCK 20 GPIO6 19 9 AGND DIN 22 BCK 21 LRCK 23 6 OUTL 8 AVDD ADR1 24 5 VNEG 7 OUTR XSMT 25 4 CAPM LDOO 26 DGND 27 2 CAPP 3 CPGND DVDD 28 1 CPVDD PCM512x (top view) Table 3.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 5.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE Supply Voltage Digital Input Voltage UNIT AVDD, CPVDD, DVDD –0.3 to 3.9 LDOO wtih DVDD at 1.8V (See Typical Applications Circuits) –0.3 to 2.25 DVDD at 1.8V –0.3 to 2.25 DVDD at 3.3V –0.3 to 3.9 Analog Input Voltage V –0.3 to 3.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless otherwise noted.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless otherwise noted.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX Gain error –6 ±2.0 6 Gain mismatch, channel-tochannel –6 ±0.5 6 –5 ±1.0 5 UNIT Analog Output Output voltage Bipolar zero error 2.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512fS and 24-bit data unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDC Power Supply Requirements DVDD Digital supply voltage Target DVDD = 1.8V 1.65 1.8 1.95 DVDD Digital supply voltage Target DVDD = 3.3V 3.0 3.3 3.6 AVDD Analog supply voltage 3.0 3.3 3.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PCM5121 THD+N vs vs Input Level PCM5122 THD+N vs vs Input Level 10 -10 -10 -30 -30 THD+N [dB] THD+N [dB] 10 -50 -50 -70 -70 -90 -90 -110 -100 -80 -60 -40 Input Level [dBFS] -20 0 -110 -100 -80 -60 -40 Input Level [dBFS] Figure 2. 0 Figure 3.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PCM5122 FFT Plot at BPZ -20 -40 -40 -60 -60 -80 -80 Amplitude [dB] Amplitude [dB] PCM5121 FFT Plot at BPZ -20 -100 -120 -100 -120 -140 -140 -160 -160 -180 -180 0 5 10 Frequency [kHz] 15 20 0 5 Figure 6.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) All specifications at TA = 25°C, AVDD = CPVDD = DVDD = 3.3V, fS = 48kHz, system clock = 512 fS and 24-bit data unless otherwise noted. PCM5122 FFT Plot at -60dB To 300kHz 0 -20 -20 -40 -40 -60 -60 Amplitude [dB] Amplitude [dB] PCM5121 FFT Plot at -60dB To 300kHz 0 -80 -100 -80 -100 -120 -120 -140 -140 -160 -160 0 50 100 150 200 Frequency [kHz] 250 300 0 50 Figure 10.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com APPLICATION INFORMATION Typical Application Circuits The PCM512x devices can be operated in a variety of configurations to support a wide range of applications. Figure 12 through Figure 21 show different combinations of power supplies, control methods, and VCOM/VREF usage. 3.3V 3.3V 1 CPVDD DVDD 28 2 CAPP DGND 27 1.8V 3.3V 1 CPVDD DVDD 28 2 CAPP DGND 27 0.1 F 0.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 1.8V 3.3V 1 CPVDD DVDD 28 2 CAPP DGND 27 1.8V 3.3V 1 CPVDD DVDD 28 2 CAPP DGND 27 3 CPGND LDOO 26 4 CAPM XSMT 25 5 VNEG MISO 24 6 OUTL LRCK 23 0.1 F 0.1 F 0.1 F 2.2 F 2.2 F 3 CPGND LDOO 26 4 CAPM XSMT 25 5 VNEG MISO 24 6 OUTL LRCK 23 7 OUTR DIN 22 8 AVDD BCK 21 9 AGND SCK 20 10 VCOM GPIO6 19 Soft mute 2.2 F C1 3.3V 10 F R2 + 0.1 F 11 MOSI MODE1 17 C1 C2 3.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com 1.8V 3.3V 1 CPVDD DVDD 28 2 CAPP DGND 27 1.8V 3.3V 1 CPVDD DVDD 28 2 CAPP DGND 27 3 CPGND LDOO 26 4 CAPM XSMT 25 Soft mute 5 VNEG ADR1 24 I2C Address 1 6 OUTL LRCK 23 0.1 F 0.1 F 0.1 F 2.2 F 2.2 F LDOO 26 4 CAPM XSMT 25 Soft mute ADR1 24 I2C Address 1 2.2 F 5 VNEG R1 6 OUTL LRCK 23 7 OUTR DIN 22 8 AVDD BCK 21 9 AGND SCK 20 C1 C2 3.3V 10 F R2 + 0.1 F PCM Audio Source 3 CPGND 2.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Analog Outputs The PCM512x devices include a two-channel DAC, with single-ended outputs. The full-scale output voltage is 2.1Vrms with ground center output. A dc-coupled load is supported in addition to an ac-coupled load, if the load resistance conforms to the specification.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Recommended Output Filter for the PCM512x The diagram in Figure 22 shows the recommended output filter for the PCM512x. The new PCM512x nextgeneration current segment architecture offers excellent out-of-band noise, making a traditional 20kHz low pass filter a thing of the past.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 3.3V 2.8V AVDD, CPVDD 1.8V 1.5V DVDD, LDOO Internal Reset Reset Removal Internal Reset 4 ms I2S Clocks SCK, BCK, LRCK Figure 24. Power-On Reset Timing, DVDD = 1.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com System Clock Input The PCM512x requires a system clock to operate the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 20) and supports up to 50MHz. The PCM512x system-clock detection circuit automatically senses the system-clock frequency. Common audio sampling frequencies of 8kHz, 16kHz, 32kHz - 44.1kHz - 48kHz, 88.2kHz - 96kHz, 176.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 System Clock PLL Mode The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the DAC. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 9. PLL Configuration Registers (continued) DLRK External LRCK Div Page 0, Register 33, D(7:0) SCK DIV BCKO Q PLLEN Q=1,2,3, ..,127,128 DIV Q Q=1,2,3, SCK MCK DIV Q Q=1,2,3, LRCKO ..,127,128 DSPCK ..,127,128 SRCREF DIV CPCK Q PLL GPIO OSC K * R /P PLLCK PLLCKIN SCK BCK GPIO Q=1,2,3, BCK DIV Q SCK K = J.D J = 1,2,3, ..,62,63 D = 0000, 0001, ., 9998, 9999 R = 1,2,3,4, .,15,16 OSCCK PLLCK Q=1,2,3, ..
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 PLL Calculation The PCM512x has an on-chip PLL with fractional multiplication to generate the clock frequency needed by the audio DAC, Negative Charge Pump, Modulator and Digital Signal Processing blocks. The programmability of the PLL allows operation from a wide variety of clocks that may be available in the system.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 10. PLL Registers Divider Function Bits PLLE PLL enable Page 0, Register 4, D(0) PPDV PLL P Page 0, Register 20, D(3:0) PJDV PLL J Page 0, Register 21, D(5:0) PDDV PLL D PRDV PLL R Page 0, Register 22, D(5:0) Page 0, Register 23, D(7:0) Page 0, Register 24, D(3:0) Table 11.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 12. Recommended Clock Divider Settings for PLL as Master Clock (VREF Mode) fS (kHz) RSCK SCK (MHz) PLL VCO (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL fS DSP fS NMAC DSP CLK (MHz) MOD fS MOD f (kHz) NDAC DOSR % Error NCP CP f (kHz) 8 128 1.024 98.304 1 1.024 96 48 2 12288 1024 12 8.192 768 6144 16 48 0 4 1536 8 192 1.536 98.304 1 1.536 64 32 2 12288 1024 12 8.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 12. Recommended Clock Divider Settings for PLL as Master Clock (VREF Mode) (continued) SCK (MHz) PLL VCO (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL fS DSP fS NMAC DSP CLK (MHz) MOD fS MOD f (kHz) NDAC DOSR % Error NCP CP f (kHz) fS (kHz) RSCK 22.05 384 8.4672 90.3168 3 2.822 32 32 1 4096 1024 4 22.5792 256 5644.8 16 16 0 4 1411.2 22.05 512 11.2896 90.3168 3 3.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 12. Recommended Clock Divider Settings for PLL as Master Clock (VREF Mode) (continued) fS (kHz) RSCK SCK (MHz) PLL VCO (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL fS DSP fS NMAC DSP CLK (MHz) MOD fS MOD f (kHz) NDAC DOSR % Error NCP CP f (kHz) 96 48 4.608 98.304 3 1.536 64 32 2 1024 512 2 49.152 64 6144 16 4 0 4 1536 96 64 6.144 98.304 1 6.144 16 8 2 1024 512 2 49.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 13. Recommended Clock Divider Settings for PLL as Master Clock (VCOM Mode) fS (kHz) RSCK SCK (MHz) PLL VCO (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL FS DSP FS NMAC DSP CLK (MHz) MOD fS MOD f (kHz) NDAC DOSR % Error NCP CP f (kHz) 8 128 1.024 73.728 1 1.024 72 36 2 9216 768 12 6.144 768 6144 12 48 0 4 1536 8 192 1.536 73.728 1 1.536 48 24 2 9216 768 12 6.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 13. Recommended Clock Divider Settings for PLL as Master Clock (VCOM Mode) (continued) SCK (MHz) PLL VCO (MHz) P PLL REF (MHz) M = K*R K = J.D R PLL FS DSP FS NMAC DSP CLK (MHz) MOD fS MOD f (kHz) NDAC DOSR % Error NCP CP f (kHz) fS (kHz) RSCK 22.05 384 8.4672 84.672 3 2.822 30 30 1 3840 960 4 21.168 256 5644.8 15 16 0 4 1411.2 22.05 512 11.2896 84.672 2 5.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 13. Recommended Clock Divider Settings for PLL as Master Clock (VCOM Mode) (continued) fS (kHz) RSCK SCK (MHz) 48 1024 49.152 73.728 8 6.144 12 12 1 1536 768 2 36.864 128 6144 12 8 0 4 1536 96 32 3.072 73.728 2 1.536 48 24 2 768 384 2 36.864 64 6144 12 4 0 4 1536 96 48 4.608 73.728 3 1.536 48 24 2 768 384 2 36.864 64 6144 12 4 0 4 1536 96 64 6.144 73.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 14. Recommended Clock Divider Settings for SCK as Master Clock fS (kHz) RSCK SCK (MHz) DSP fS NMAC DSP CLK (MHz) MOD fS MOD f (kHz) NDAC DOSR NCP CP f (kHz) 8 256 2.048 256 1 2.048 256 2048 1 16 2 1024 8 384 3.072 384 1 3.072 384 3072 1 24 2 1536 8 512 4.096 512 1 4.096 512 4096 1 32 2 2048 8 768 6.144 768 1 6.144 768 6144 1 48 4 1536 8 1024 8.192 1024 1 8.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 14. Recommended Clock Divider Settings for SCK as Master Clock (continued) 34 fS (kHz) RSCK SCK (MHz) DSP fS NMAC DSP CLK (MHz) MOD fS MOD f (kHz) NDAC DOSR NCP CP f (kHz) 192 128 24.576 128 1 24.576 32 6144 4 2 4 1536 192 192 36.864 192 1 36.864 32 6144 6 2 4 1536 192 256 49.152 256 1 49.152 32 6144 8 2 4 1536 384 64 24.576 64 1 24.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Audio Data Interface Audio Serial Interface The audio interface port is a 3-wire serial port with the signals LRCK (pin 15), BCK (pin 13), and DIN (pin 14). BCK is the serial audio bit clock, used to clock the serial data present on DIN into the serial shift register of the audio interface. Serial data is clocked into the PCM512x on the rising edge of BCK. LRCK is the serial audio left/right word clock. Table 15.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com PCM Audio Data Formats and Timing The PCM512x supports industry-standard audio data formats, including standard I2S and left-justified. Data formats are selected using the FMT (pin 16), Low for I2S, and High for Left-justified. All formats require binary 2scomplement, MSB-first audio data; up to 32-bit audio data is accepted. The PCM512x also supports right-justified and TDM in software control mode.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 The I2S master timing is shown in Figure 28 and Table 18. t BCH t BCL 0. 5 * DVDD BCK ( Output) t LRD tBCY LRCK 0. 5 * DVDD ( Output) t DOD DATA 0. 5 * DVDD ( Output) tDS tDH DATA 0. 5 * DVDD ( Input) Figure 28. PCM512x Serial Audio Timing - Master Table 18.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com 1tS R-channel L-channel LRCK BCK Audio data word = 16-bit, BCK = 32, 48, 64fS 1 2 15 16 1 2 15 16 DATA MSB LSB MSB LSB 2 23 Audio data word = 24-bit, BCK = 48, 64fS - , 1 2 2 24 1 24 DATA MSB LSB MSB LSB Audio data word = 32-bit, BCK = 64fS 1 2 31 32 1 2 31 32 DATA MSB LSB MSB LSB Figure 29.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 The following data formats are only available in software mode. Right Justified Data Format; L-channel = HIGH, R-channel = LOW Figure 31. Right Justified Audio Data Format TDM Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 0 Figure 32.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com TDM Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = 1 Figure 33. TDM 2 Audio Data Format TDM Data Format; L-channel = FIRST, R-channel = LAST with OFFSET = N Figure 34.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Function Descriptions PCM512x Audio Processing Overview The PCM512x supports a fixed audio processing flow with programmable coefficients. (Program 5 - Fixed Audio Processing Flow (Program 5) of this datasheet). Details can be found below.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Interpolation Filter The PCM512x provides 4 types of interpolation filters, selectable by writing to Page 0, Register 43, D(4:0). Table 19.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 21. Normal x8 Interpolation Filter, Single Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Value (Typical) Filter Gain Stop Band 0.55fS ….. 7.455fS Value (Max) Units dB dB Filter Group Delay 20/fS S 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.4 4 0 50 100 150 200 250 Samples 300 350 G023 G012 Figure 35.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 22. Normal x4 Interpolation Filter, Dual Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Filter Gain Stop Band 0.55fS ….. 3.455fS Value (Typical) Value (Max) Units dB dB Filter Group Delay 20/fS 0 S 1.0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.4 4 0 20 40 60 80 100 Samples G009 Figure 38.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 23. Normal x2 Interpolation Filter, Quad Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Value (Typical) Filter Gain Stop Band 0.55fS ….. 1.455fS Value (Max) Units dB dB Filter Group Delay 20/fS 0 S 1.0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.4 4 0 10 20 30 40 50 60 Samples 70 80 90 G006 Figure 41.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 24. Low latency x8 Interpolation Filter, Single Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Value (Typical) Value (Max) Units dB Filter Gain Stop Band 0.55fS ….. 7.455fS dB Filter Group Delay S 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 0.0 −80 −0.2 −100 −0.4 −120 0 1 2 Frequency (x fS) 3 4 −0.6 0 50 100 150 200 250 Samples G011 Figure 44.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 25. Low latency x4 Interpolation Filter, Dual Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Value (Typical) Value (Max) dB Filter Gain Stop Band 0.55fS ….. 3.455fS dB Filter Group Delay Units S 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 0.0 −80 −0.2 −100 −0.4 −120 0 1 2 Frequency (x fS) 3 4 −0.6 0 20 40 60 80 100 Samples 120 140 160 G008 Figure 47.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 26. Low latency ×2 Interpolation Filter, Quad Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Value (Typical) Value (Max) dB Filter Gain Stop Band 0.55fS ….. 1.455fS dB Filter Group Delay Units S 0 1.0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 4 −0.4 0 10 20 30 40 50 60 Samples G005 Figure 50.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 27. Asymmetric FIR x8 Interpolation Filter, Single Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.40fS Value (Typical) Filter Gain Stop Band 0.72fS ….. 7.28fS Filter Group Delay 0 Value (Max) Units ±0.05 dB –50 dB 1.2tS S 1 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0 −100 −120 −0.2 0 1 2 Frequency ( × fS) 3 −0.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 28. Asymmetric FIR x4 Interpolation Filter, Dual Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.40fS Filter Gain Stop Band 0.72fS ….. 3.28fS Value (Typical) Filter Group Delay 0 Value (Max) Units ±0.05 dB –50 dB 1.2tS S 1 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0 −100 −120 −0.2 0 1 2 Frequency ( × fS) 3 −0.4 4 0 10 20 30 Samples 40 G002 Figure 56.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 29. Asymmetric FIR x2 Interpolation Filter, Quad Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.40fS Value (Typical) Filter Gain Stop Band 0.72fS ….. 1.28fS Filter Group Delay 0 Value (Max) Units ±0.05 dB –50 dB 1.2tS S 1 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0 −100 −120 −0.2 0 1 2 Frequency ( × fS) 3 −0.4 4 0 10 20 30 40 50 Samples G001 Figure 59.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 30. High-Attentuation x8 Interpolation Filter, Single Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Value (Typical) Filter Gain Stop Band 0.55fS ….. 7.455fS Filter Group Delay 0 Value (Max) Units ±0.0005 dB –100 dB 33.7tS S 1 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0 −100 −120 −0.2 0 1 2 Frequency ( × fS) 3 −0.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 31. High-Attentuation x4 Interpolation Filter, Dual Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Filter Gain Stop Band 0.55fS ….. 3.455fS Value (Typical) Filter Group Delay 0 Value (Max) Units ±0.0005 dB –100 dB 33.7tS S 1 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0 −100 −120 −0.2 0 1 2 Frequency ( × fS) 3 −0.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 32. High-Attentuation x2 Interpolation Filter, Quad Rate Parameter Condition Filter Gain Pass Band 0 ……. 0.45fS Value (Typical) Filter Gain Stop Band 0.55fS ….. 1.455fS Filter Group Delay 0 Value (Max) Units ±0.0005 dB –100 dB 33.7tS S 1 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0 −100 −120 −0.2 0 1 2 Frequency ( × fS) 3 −0.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Fixed Audio Processing Flow (Program 5) The PCM512x family implements signal processing capabilities and interpolation filtering via processing blocks. These fixed processing blocks give users the choice of how much and what type of signal processing they may use and which interpolation filter is applied.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Figure 72 shows a screen capture of PurePath Studio. Figure 72. PurePath Studio Screen Capture Biquad Section The transfer function of each of the biquad filters is given by H (z ) = N 0 + 2 N 1z - 1 + N 2 z - 2 2 2 3 - 2 D 1z - 1 - D 2 z - 2 (2) N0 + Z-1 Z-1 N1*2 D1*2 N2 D2 Z-1 Z-1 Figure 73. Biquad Block Table 33.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 33.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 33. Biquad Filter Coefficients (continued) Filter Channel Coefficient Register N0 C65 (Pg 46, Reg 28, 29, 30, 31) N1 C66 (Pg 46, Reg 32, 33, 34, 35) N2 C67 (Pg 46, Reg 36, 37, 38, 39) D1 C68 (Pg 46, Reg 40, 41, 42, 43) D2 C69 (Pg 46, Reg 44, 45, 46, 47) Lch, Rch BIQUAD (7) - 2 BIQUAD (8) - 2 Dynamic Range Compression Dynamic range compression (DRC) improves the overall listening experience.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 34.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 34.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 36. Stereo Multiplexer Select Coefficient Coefficient Register Stereo_Mux_1_MuxSelect C152 (Pg 49, Reg 16, 17, 18, 19) Description Table 37. Stereo Multiplexer Input Coefficient Coefficient Register C_to_D_1_Coefval C_to_D_2_Coefval Description C153 (Pg 49, Reg 20, 21, 22, 23) Mono Mixer The Mono Mixer computes a weighted sum of 2 input channels and produces an output.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Miscellaneous Coefficients Table 40.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 42. Ramp Up or Down Frequency (continued) 11 Direct change 11 Direct change Table 43. Ramp Up or Down Step Ramp down step Step dB 4.0 00 -4.0 2.0 01 -2.0 10 -1.0 11 -0.5 Ramp up step Step dB 00 01 10 1.0 11 0.5 Comments Default Comments Default Emergency Ramp Down Digital volume emergency ramp down by is provided for situations such as I2S clock error and power supply failure.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Power Save Modes The PCM512x offers two power-save modes; standby and power-down. When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM512x automatically enters standby mode. The DAC and line driver are also powered down. The device can also be placed in standby mode via software command. When BCK and LRCK remain at a low level for more than 1 second, the PCM512x automatically enters powerdown mode.
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PCM5121, PCM5122 www.ti.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com External Power Sense Undervoltage Protection mode (supported only when DVDD = 3.3V) The XSMT pin can also be used to monitor a system voltage, such as the 24VDC LCD TV backlight, or 12VDC system supply using a voltage divider created with two resistors. (See Figure 78 ) • If the XSMT pin makes a transition from “1” to “0” over 6ms or more, the device switches into external undervoltage protection mode.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Recommended Powerdown Sequence With inadequate system design, the PCM512x can exhibit some pop on power down. Pops are caused by the device not having enough time to detect power loss and start the muting process. The PCM512x evaluation board avoids audible pop with an electrolytic decoupling capacitor.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com 2. Stop I2S clocks (SCK, BCK, LRCK) 3ms before powerdown as shown below: 3.3V VDD 0V High XSMT Low 3msec High I2S Clocks SCK, BCK, LRCK Low Time Unplanned Shutdown Many systems use a low-noise regulator to provide an AVDD 3.3V supply for the DAC. The XSMT Pin can take advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the DAC before the entire SMPS discharges.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Register Read/Write Operation All read/write operations for the serial control port use 16-bit data words. Figure 81 shows the control data word format. The most significant bit is the read/write bit. For write operations, the bit must be set to 0. For read operations, the bit must be set to 1. There are seven bits, labeled IDX[6:0], that hold the register index (or address) for the read and write operations.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com MS MC A6 MOSI A5 A4 A3 A2 A1 A0 HI-Z MISO R D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 HI-Z Figure 84. Serial Control Format; Read MS MC MOSI ADDR BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 R HI-Z HI-Z MISO Figure 85. Serial Control Format; Read, Multiple Byte Figure 86.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 47. Control Interface Timing (1) Parameters Min tMCY MC Pulse Cycle Time 100 tMCL MC Low Level Time 40 tMCH MC High Level Time 40 tMHH MS High Level Time 20 tMSS MS ↓ Edge to MC ↑ Edge 30 (1) tMSH MS Hold Time tMDH MDI Hold Time 15 tMDS MDI Set-up Time 15 tMOS MC Rise Edge to MDO Stable Max Units ns 30 20 MC falling edge for LSB to MS rising edge.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com I2C Interface The PCM512x supports the I2C serial bus and the data transmission protocol for standard and fast mode as a slave device. This protocol is explained in the I2C specification 2.0. In I2C mode, the control terminals are changed as follows. Table 48.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Table 50. Write Operation - Basic I2C Framework Transmitter M M M S M S M S S M Data Type St slave address R/ ACK DATA ACK DATA ACK ACK Sp Table 51.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 54.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 PCM512x Register Map In any page, register 0 is the Page Select Register. The register value selects the Register Page from 0 to 255 for next read or write command. Table 55. Register Map Summary (continued) Table 55.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Table 56. Coefficient Buffer-A Map (continued) .. .. .. .. .. .. .. C119 47 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C120 48 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. .. .. .. .. .. .. .. C149 48 124 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. C150 49 8 Coef(23:16) Coef(15:8) Coef(7:0) Reserved. .. .. .. .. .. .. ..
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Detailed Register Descriptions Page 0 / Register 1 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 1 01 RSV RSV RSV RSTM RSV RSV RSV RSTR Reset Value RSV 0 0 Reserved Reserved. Do not access. RSTM Reset Modules This bit resets the interpolation filter and the DAC modules. Since the DSP is also reset, the coeffient RAM content will also be cleared by the DSP. This bit is auto cleared and can be set only in standby mode.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 RSV www.ti.com Reserved Reserved. Do not access. RQML Mute Left Channel This bit issues soft mute request for the left channel. The volume will be smoothly ramped down or up to avoid pop or click noise. Default value: 0 0: Normal volume 1: Mute RQMR Mute Right Channel This bit issues soft mute request for the right channel. The volume will be smoothly ramped down or up to avoid pop or click noise.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Page 0 / Register 7 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 7 07 RSV RSV RSV DEMP RSV RSV RSV SDSL Reset Value RSV 0 0 Reserved Reserved. Do not access. DEMP De-Emphasis Enable This bit enables or disables the de-emphasis filter. The default coefficients are for 44.1kHz sampling rate, but can be changed by reprogramming the appropriate coeffients in RAM.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com 0: GPIO2 is input 1: GPIO2 is output G1OE GPIO1 Output Enable This bit sets the direction of the GPIO1 pin Default value: 0 0: GPIO1 is input 1: GPIO1 is output Page 0 / Register 9 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 9 09 RSV RSV BCKP BCKO RSV RSV RSV LRKO 0 0 Reset Value RSV 0 Reserved Reserved. Do not access. BCKP BCK Polarity This bit sets the inverted BCK mode.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 RSV Reserved Reserved. Do not access. RBCK Master Mode BCK Divider Reset This bit, when set to 0, will reset the SCK divider to generate BCK clock for I2S master mode. To use I2S master mode, the divider must be enabled and programmed properly.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 RSV www.ti.com Reserved Reserved. Do not access. PJDV[5:0] PLL J These bits set the J part of the overall PLL multiplication factor J.D * R.These bits are ignored in clock auto set mode. Default value: 000000 000000: Prohibited (do not set this value) 000001: J=1 000010: J=2 ...
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Page 0 / Register 27 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 27 1B RSV DDSP6 DDSP5 DDSP4 DDSP3 DDSP2 DDSP1 DDSP0 0 0 0 0 0 0 0 Reset Value RSV Reserved Reserved. Do not access. DDSP[6:0] DSP Clock Divider These bits set the source clock divider value for the DSP clock. These bits are ignored in clock auto set mode. Default value: 0000000 0000000: Divide by 1 0000001: Divide by 2 ...
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 RSV www.ti.com Reserved Reserved. Do not access. DOSR[6:0] OSR Clock Divider These bits set the source clock divider value for the OSR clock. These bits are ignored in clock auto set mode. Default value: 0000000 0000000: Divide by 1 0000001: Divide by 2 ...
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PCM5121, PCM5122 www.ti.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com This bit controls whether to ignore the LRCK or BCK missing detection. The LRCK or BCK need to be in low state (not only static) to be deemed missing. When ignored an LRCK or BCK missing will not cause the DAC go into powerdown mode. Default value: 0 0: Regard LRCK or BCK missing detection 1: Ignore LRCK or BCK missing detection DCAS Disable Clock Divider Autoset This bit enables or disables the clock auto set mode.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 00000000: offset = 0 BCK (no offset) 00000001: ofsset = 1 BCK 00000010: offset = 2 BCKs 11111111: offset = 256 BCKs Page 0 / Register 42 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 42 2A RSV RSV AUPL1 AUPL0 RSV RSV AUPR1 AUPR0 0 1 0 1 Reset Value RSV Reserved Reserved. Do not access. AUPL[1:0] Left DAC Data Path These bits control the left channel audio data path connection.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Page 0 / Register 44 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 44 2C RSV RSV RSV RSV RSV CMDP2 CMDP1 CMDP0 0 0 0 Reset Value RSV Reserved Reserved. Do not access. CMDP[2:0] Clock Missing Detection Period These bits set how long both BCK and LRCK keep low before the audio clocks deemed missing and the DAC transitions to powerdown mode.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Page 0 / Register 60 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 60 3C RSV RSV RSV RSV RSV RSV PCTL1 PCTL0 0 0 Reset Value RSV Reserved Reserved. Do not access. PCTL[1:0] Digital Volume Control These bits control the behavior of the digital volume.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Page 0 / Register 63 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 63 3F VNDF1 VNDF0 VNDS1 VNDS0 VNUF1 VNUF0 VNUS1 VNUS0 0 0 1 0 0 0 1 0 Reset Value VNDF[1:0] Digital Volume Normal Ramp Down Frequency These bits control the frequency of the digital volume updates when the volume is ramping down.The setting here is applied to soft mute request, asserted by XSMUTE pin or Page 0 / Register 3.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 10: Update every 4 sample periods 11: Directly set the volume to zero (Instant mute) VEDS[1:0] Digital Volume Emergency Ramp Down Step These bits control the step of the digital volume updates when the volume is ramping down due to clock error or power outage, which usually needs faster ramp down compared to normal soft mute.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 RSV Reserved Reserved. Do not access. G3SL[3:0] GPIO3 Output Selection These bits select the signal to output to GPIO3. To actually output the selected signal, the GPIO3 must be set to output mode at Page 0 / Register 8.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com Page 0 / Register 84 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 84 54 RSV RSV RSV RSV G5SL3 G5SL2 G5SL1 G5SL0 0 0 0 0 Reset Value RSV Reserved Reserved. Do not access. G5SL[3:0] GPIO5 Output Selection These bits select the signal to output to GPIO5. To actually output the selected signal, the GPIO5 must be set to output mode at Page 0 / Register 8.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 1011: Charge pump clock 1100: Reserved 1101: Reserved 1110: Under voltage flag, asserted when XSMUTE voltage is higher than 0.7 DVDD 1111: Under voltage flag, asserted when XSMUTE voltage is higher than 0.3 DVDD Page 0 / Register 86 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 86 56 RSV RSV GOUT5 GOUT4 GOUT3 GOUT2 GOUT1 GOUT0 0 0 0 0 0 0 Reset Value RSV Reserved Reserved. Do not access.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 www.ti.com 1: Overflow occurred R2OV Right2 Overflow (Read Only) The bit indicates whether the right channel of DSP second output port has overflow. This bit is sticky and is cleared when read. 0: No overflow 1: Overflow occurred SFOV Shifter Overflow (Read Only) This bit indicates whether overflow occurred in the DSP shifter (possible sample corruption). This bit is sticky and is cleared when read.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 Page 0 / Register 93 93 5D DTBR7 DTBR6 DTBR5 DTBR4 DTBR3 DTBR2 DTBR1 DTBR0 Reset Value RSV Reserved Reserved. Do not access. DTBR[8:0] Detected BCK Ratio (MSB) (Read Only) These bits indicate the currently detected BCK ratio, that is, the number of BCK clocks in one audio frame. Note that for the extreme case of BCK = 1 fS (not a usable scenario), the detected ratio will be unreliable.
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 RSV www.ti.com Reserved Reserved. Do not access. AMFL Auto Mute Flag for Left Channel (Read Only) This bit indicates the auto mute status for left channel. 0: Not auto muted 1: Auto muted AMFR Auto Mute Flag for Right Channel (Read Only) This bit indicates the auto mute status for right channel.
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PCM5121, PCM5122 www.ti.com SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 RSV Reserved Reserved. Do not access. UEPD External UVP Control This bit enables or disables detection of power supply drop via XSMUTE pin (External Under Voltage Protection). Default value: 0 0: Enabled 1: Disabled UIPD Internal UVP Control This bit enables or disables internal detection of AVDD voltage drop (Internal Under Voltage Protection).
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PCM5121, PCM5122 SLAS763A – AUGUST 2012 – REVISED SEPTEMBER 2012 RSV www.ti.com Reserved Reserved. Do not access. RCMF VCOM Reference Ramp Up This bit controls the VCOM voltage ramp up speed. Default value: 0 0: Normal ramp up, ~600ms with external capacitance = 1uF 1: Fast ramp up, ~3ms with external capacitance = 1uF Page 1 / Register 9 Dec Hex b7 b6 b5 b4 b3 b2 b1 b0 9 09 RSV RSV RSV RSV RSV RSV RSV VCPD Reset Value RSV 1 Reserved Reserved. Do not access.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM5121PWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 PCM5122PWR TSSOP PW 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM5121PWR TSSOP PW 28 2000 367.0 367.0 38.0 PCM5122PWR TSSOP PW 28 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.