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PCM9211

www.ti.com

SBAS495 –JUNE 2010

216-kHz Digital Audio Interface Transceiver (DIX)

with Stereo ADC and Routing

Check for Samples: PCM9211

FEATURES

• Other Function Features:

23456

• Integrated DIX, ADC, and Signal Routing:

– Power Down (Pin and Register Control)

– Asynchronous Operation (DIR, DIT, ADC) – PCM Port Sampling Frequency Counter

– Mux and Routing of PCM Data: – GPIO and GPO

– I

S™, Left-Justified, Right-Justified – OSC for External Crystal (24.576 MHz)

– Multipurpose Input/Output Pins – SPI™, I

C™ or Hardware Control Modes

• Digital Audio I/F Receiver (DIR): • Power Supply:

– 24-bit, 216-kHz Capable – 3.3 V (2.9 V to 3.6 V) for DIX, All Digital

– 50-ps Ultralow Jitter – 5 V (4.5 V to 5.5 V) for ADC Analog

– Non-PCM Detection (IEC61937, DTS-CD/LD) • Operating Temperature: –40°C to +85°C

– 12x S/PDIF Input Ports: • Package: 48-Pin LQFP

– 2x Coaxial S/PDIF Inputs

APPLICATIONS

– 10x Optical S/PDIF Inputs

• Home Theater and AVR Equipment

• Digital Audio I/F Transmitter (DIT):

• Television and Soundbars

– 24-Bit, 216-kHz Capable

• Musical Instruments, Recording, and

– 24-Bit Data Length

Broadcast

– 48-Bit Channel Status Buffer

• High-Performance Soundcards

– Synchronous/Asynchronous Operation

DESCRIPTION

• Analog-to-Digital Converter (ADC):

– 24-Bit, 96-kHz Capable The PCM9211 is a complete analog and digital

front-end for today's multimedia players and

– Dynamic Range: 101 dB (f

= 96 kHz)

recorders.

– Synchronous/Asynchronous Operation

The PCM9211 integrates a stereo ADC, S/PDIF

• Routing Function:

transceiver with up to 12 multiplexed inputs and 3x

– Input: 3x PCM, 1x DIR, 1x ADC

PCM inputs to allow other audio receivers to be

– Output: Main Out, Aux Out, DIT multiplexed along with the analog and S/PDIF signals

to a digital signal processor (DSP).

– Multi-Channel (8-Ch) PCM Routing

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2AC-3 is a trademark of Dolby Laboratories.

3SPI is a trademark of Motorola, Inc.

S, I

C are trademarks of NXP Semiconductors.

5TOSLINK is a trademark of Toshiba Corp.

6All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (121 pages)

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PCM9211 www.ti.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 RECOMMENDED OPERATING CONDITIONS (continued) Over operating free-air temperature range (unless otherwise noted). MIN NOM MAX UNIT Analog input level VINL, VINR 3 Digital output load capacitance Except SCKO 20 VPP pF Digital output load capacitance SCKO 10 pF 10 pF +85 °C MODE pin capacitance Operating free-air temperature –40 +25 ELECTRICAL CHARACTERISTICS: GENERAL All specifications at TA = +25°C, VCC = VDD = VDDRX = 3.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com ELECTRICAL CHARACTERISTICS: GENERAL (continued) All specifications at TA = +25°C, VCC = VDD = VDDRX = 3.3 V, and VCCAD = 5 V, unless otherwise noted. PCM9211 PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT VCC 2.9 3.3 3.6 VDC VDD 2.9 3.3 3.6 VDC 4.5 5.0 5.5 VDC 2.9 3.3 3.6 VDC POWER-SUPPLY REQUIREMENTS VCCAD Voltage range VDDRX fS = 48 kHz / DIR, fS = 48 kHz / ADC, fS = 48 kHz / DIT ICC Supply current 4.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 ELECTRICAL CHARACTERISTICS: Analog-to-Digital Converter (ADC) All specifications at TA = +25°C, VCC = VDD = VDDRX = 3.3 V, and VCCAD = 5 V, unless otherwise noted. PCM9211 PARAMETER TEST CONDITIONS MIN TYP 16 24 MAX UNIT ADC, CHARACTERISTICS Resolution fS Sampling frequency Bit clock frequency System clock frequency Bits 16 96 kHz 64fS 1.024 6.144 MHz 256fS 4.096 24.576 MHz 512fS 8.192 24.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com ELECTRICAL CHARACTERISTICS: Digital Audio I/F Receiver (DIR) All specifications at TA = +25°C, VCC = VDD = VDDRX = 3.3 V, and VCCAD = 5 V, unless otherwise noted. PCM9211 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIR, COAXIAL INPUT AMPLIFIER (RXIN0 and RXIN1) Input resistance 20 Input voltage kΩ 0.
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PCM9211 www.ti.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com PIN FUNCTIONS (continued) PIN NO. (2) (3) (4) (5) 8 NAME I/O 5-V TOLERANT DESCRIPTION 16 MPO1 O No Multipurpose output 1 17 DOUT O No Main output port, serial digital audio data output 18 LRCK O No Main output port, LR clock output 19 BCK O No Main output port, Bit clock output 20 SCKO O No Main output port, System clock output 21 DGND – – Ground, for digital 22 DVDD – – Power supply, 3.3 V (typ.
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PCM9211 www.ti.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS: ADC All specifications at TA = +25°C, VCCAD = 5 V, VDD = 3.3 V, fS = 48 kHz, SCK = 512fS, and 24-bit data, unless otherwise noted.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 TYPICAL CHARACTERISTICS: ADC (continued) All specifications at TA = +25°C, VCCAD = 5 V, VDD = 3.3 V, fS = 48 kHz, SCK = 512fS, and 24-bit data, unless otherwise noted. ADC OUTPUT SPECTRUM OUTPUT SPECTRUM (–60 dB, N = 32,768) 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) OUTPUT SPECTRUM (–1 dB, N = 32,768) -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 0 5 10 15 20 0 5 Frequency (kHz) 10 15 20 Frequency (kHz) Figure 5. Figure 6.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com TYPICAL CHARACTERISTICS: ADC (continued) All specifications at TA = +25°C, VCCAD = 5 V, VDD = 3.3 V, fS = 48 kHz, SCK = 512fS, and 24-bit data, unless otherwise noted. ANTIALIASING FILTER CHARACTERISTIC 0 -5 -5 -10 -10 -15 -15 Amplitude (dB) Amplitude (dB) HIGH-PASS FILTER CHARACTERISTIC 0 -20 -25 -30 -20 -25 -30 -35 -35 -40 -40 -45 -45 -50 0 0.1 0.2 0.3 0.4 -50 1 Normalized Frequency (x fS/1000) Figure 9.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 OVERVIEW Introduction The PCM9211 is an analog and digital front-end device for any media player/recorder. It integrates a 216-kHz Digital Audio Transceiver (DIX), a 96-kHz stereo ADC, and multiple PCM (I2S, Left-Justified, Right-Justified) interfaces.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com The PCM9211 has two RECOUT signals that can be routed to the MPO port. The respective sources can be drawn from one of the 12 S/PDIF inputs, or the DIT module. Channel status, user data, and valid audio data from the S/PDIF stream can be found in various registers or routed to MPIO pins. In addition, the block start signal can be routed to an I/O pin, so that any postprocessing DSP can be informed of the start of a frame for decoding data and so forth.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Auxiliary PCM Audio Input and Output (I/O) There are up to 3x digital auxiliary (AUX) inputs and one AUX output on the PCM9211. These I/Os are multiplexed and shared with RXIN4 through RXIN7, MPIOB, and MPIOC. Each input and output supports a four-wire digital audio interface that is similar to the I2S protocol. Each I/O can support SCK (system clock), BCK (bit clock), LRCK (left/right clock, or word clock) and data transmissions.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com PCM9211 MODULE DESCRIPTIONS Power Supply The PCM9211 has four power-supply pins and four ground pins. All ground pins (AGND, AGNDAD, DGND, and GNDRX) must be connected as closely as possible to the PCM9211. The PCM9211 DVDD and DGND pins are power-supply pins that support all the onboard digital circuitry for the PCM9211. DVDD should be connected to a 3.3-V supply. DVDD drives the internal power-on reset circuit, making it a startup requirement.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Table 1 shows the timing requirements to reset the device using the RST pin. Table 1. Timing Requirements for RST Pin Device Reset SYMBOL tRSTL DESCRIPTION MIN RST pulse width (RST pin = low) TYP MAX 1 UNITS µs The condition of each output pins during the device reset is shown in Table 2. Table 2.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Figure 12 illustrates these formats.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 ADC Details System Clock The system clock for the ADC of the PCM9211 must be either 256fS or 512fS, where fS is the audio sampling rate for the ADC (16 kHz to 96 kHz). Table 3 lists the typical system clock frequencies fSCK for common audio sampling rates. Figure 13 shows the timing requirements for the system clock inputs. Table 3. ADC Clock Requirements BIT CLOCK FREQUENCY SYSTEM CLOCK FREQUENCY SAMPLING FREQUENCY 64fS 256fS 512fS 16 kHz 1.024 MHz 4.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com ADC: Clock Source Configuration A number of clock sources for the ADC are provided. Clock source selection is done using the ADCLK[2:0] register (Register 42h). In most applications, the onboard clock (XTI) is used, but using another clock source (such as a DIR recovered clock or AUXIN clock) is also possible. The ADC can only be used in a slave mode unless it is set to run in standalone mode. 1.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Additional ADC Functions The onboard ADC has some additional functions. Control of these functions is done using several registers (Register 40h through Register 49h). Each ADC channel has a digital attenuator function. The level of attenuation can be set from 20 dB to –100 dB in 0.5-dB steps, and also set to infinite attenuation (mute). By default, the digital gain/attenuation is moved 0.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com ADC: Audio Interface Mode and Timing The digital audio data can be interfaced in either slave or master mode. The interface mode is selected by using the serial mode control described in the Serial Control Mode section. The default mode is slave mode. Master mode is available only for ADC standalone operation by setting Register 6Fh/MPCSEL. In slave mode, BCK and LRCK are inputs to the ADC. BCK must be 64fS. DOUT changes on the falling edge of BCK.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 In master mode, BCK and LRCK are output from the ADC of PCM9211. BCK and LRCK are generated by the internal ADC from SCKI, and BCK is fixed as 64fS. DOUT changes on the falling edge of BCK. The detailed timing specification is shown in Figure 16. t BCH t BC L BCK (OUTPUT) 0.5 VDD t LRD t BC Y LRCK (OUTPUT) 0.5 VDD t DOD 0.5 VDD DOUT SYMBOL tBCY tBCH BCK cycle time BCK high time 0.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com STATE of SYNCHRONIZATION synchronous Asynchronous synchronous within 2 /f S t ADCDLY 3 32/f S Undefined data ADC DOUT Normal ZERO Normal Figure 17. ADC Output for Lost Synchronization Setting the ADC Sampling Frequency with XTI as Clock Source Register 31h holds the bytes that control the dividers used to bring the high-speed, 24.567-MHz clock down to SCK, BCK, and LRCK as used by the ADC.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 ADC Level Detect and Interrupt The PCM9211 has the ability to monitor audio inputs, which can be used to trigger interrupt outputs on port INT1. The ADC has a level monitor that can be set so that INT1 can be triggered whenever a specific level (referenced to 0dBFS) is crossed. A block diagram for this function is shown in Figure 18.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com The trigger threshold for the ADC can be configured at four different levels below full scale using the ADLVLTH[1:0] bits in Register 2Eh. The output is post-ADC volume control, allowing finer gain steps to be configured by changing the ADC volume control. In a typical application, this level change is done as the system moves into standby, and reset back to 0dB attenuation when the system wakes up.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 PLL Clock Source (Built-in PLL and VCO) Details The PCM9211 an has on-chip PLL (including a voltage-controlled oscillator, or VCO) for recovering the clock from the S/PDIF input signal. The VCO-derived clock is identified as the PLL clock source. When locked, the onboard PLL generates a system clock that synchronizes with the input biphase signal. When unlocked, the PLL generates its own free-run clock (from the VCO).
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PCM9211 SBAS495 – JUNE 2010 www.ti.com DIR and PLL Loop Filter Details The PCM9211 incorporates a PLL for generating clocks synchronized with the input biphase signal (S/PDIF). The onboard PLL requires an external loop filter. The components and configuration shown in Figure 20 and Table 6 are recommended for optimal performance, with these considerations: • The resistor and capacitors that configure the filter should be located and routed as close as possible to the PCM9211.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Figure 21 illustrates the connections for the XTI and XTO pins for both a resonator connection and an external clock input connection. CL1 CL2 Crystal OSC Circuit Resonator XTI RD Crystal OSC Circuit 24.576 MHz Internal Clock XTO 24.576 MHz Internal Clock XTI External Clock XTO Must be open (Optional) PCM9211 PCM9211 Resonator Connection External Clock Input Connection Figure 21.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Figure 22 shows the latency time between the input biphase signal and LRCKO/DOUT. Figure 23 illustrates the DIR decoded audio data output timing. Biphase Signal (IN) 0R W 0L B M 1L W 1R tLATE BFRAME (OUT) LRCK (OUT) 2 (I S) LRCK (OUT) 2 (All except I S) DATA (OUT) 0L 0R 1L 1R 17±1BCK SYMBOL tLATE DESCRIPTION MIN LRCKO/DOUT latency TYP 4/fS MAX UNITS s Figure 22.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Channel Status Data, User Data, and Validity Flag The PCM9211 can output decoded channel status data, user data, and a validity flag synchronized with audio data from the input S/PDIF signal. These signals can be transmitted from any of the three MPIOs (MPIO_A, MPIO_B, or MPIO_C). To assign this function to the MPIOs, see the MPIO section. Each type of output data has own dedicated output pin: • Channel status data (C) are output through MPIOs assigned as COUT.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com DIR: Parity Error Processing Error detection and processing for parity errors behave in the following manner: • For PCM data, when an error is detected (for example, a parity error), then the data from the previous sample are repeated. This sequence is shown in Figure 26, where sample Ln+1 is repeated because the incoming data (Ln+2) had an error. • For non-PCM data, the data are output as is with no changes.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Upon receipt of an interrupt source (such as fS Calculator Complete), INT0 or INT1 performs a bitwise evaluation of AND (&) with an inverted mask [Register 2Ah (INT0) and Register 2Bh (INT1)], then perform an eight-way OR of the data. If the output is '1', then INTx is set to '1', which can be used to trigger an interrupt in the host DSP. The host can then poll the INTx register to determine the interrupt source.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com There are several allowable error sources from the DIR: • Change of incoming S/PDIF sample frequency (Register 25h / EFSCHG) • Out-of-range incoming S/PDIF signal (Register 25h / EFSLMT) • Non-PCM data (Register 25h / ENPCM) • Data invalid flag is the stream (Validity bit = '1') (Register 25h / EVALID) • Parity error (Register 25h / EPARITY) • PLL unlock (default) (Register 25h / EUNLOCK) The error sources can be selected using Register 25h.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 The relationship between SFSOUT[3:0] outputs and the range of sampling frequency fS is shown in Table 8. Table 8. Calculated Biphase Sampling Frequency Output SFSOUT3 SFSOUT2 SFSOUT1 SFSOUT0 Out of range Out of range 0 0 0 0 8 kHz 7.84 kHz to 8.16 kHz 0 0 0 1 11.025 kHz 10.8045 kHz to 11.2455 kHz 0 0 1 0 12 kHz 11.76 kHz to 12.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com DIR: Audio Port Sampling Frequency Calculator The second sampling frequency calculator can be used to calculate the sampling frequency of DIR, ADC, AUXIN0, AUXIN1, AUXIN2, Main Output Port, AUX Output Port, and DIT Input. Figure 29 illustrates the sampling frequency calculator sources.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 OUTPUT REGISTER CONSTRUCTION The output 8-bit register is subdivided into three sections. The first four bits show the decoded result. The next three bits signify the source; the final bit signifies the calculator status (finished or not). The lock range of the counter (to the specified fS given in Table 9) are any clock rate within ±2%. The relation between the nominal fS and actual measured fS range is shown in Table 9. Table 9.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com DIR: Auto Source Selector for Main Output and AUX Output The AUTO source selector is an automatic system that selects the DIR or ADC output based on specific DIR conditions set by Register 26h. The AUTO source selector is integrated in both the Main Port and the AUX output separately. The typical behavior for the AUTO source selector is shown in Figure 30. This example is the default register setting for Register 26h.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Figure 31 shows the Clock Tree Diagram for the AUTO source selector. AUTO select signal defined by DIR REG.25h excluding AERROR. ERROR defined by REG.25h SCK/BCK/LRCK/DOUT REG.26h/AERROR SCK/BCK/LRCK REG.40h/ADDIS AUTO selector Main Port REG.42h/ADCKOUT ADC AUXINx REG.26h/ACKSL REG.6Bh/ MOSSRC&MOPSRC SCK/BCK/LRCK AUXINx REG.42 h /ADCLK SCK/BCK/LRCK OSC Divider Figure 31.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Digital Audio Interface Transmitter Overview The PCM9211 has an onboard Digital Audio Interface Transmitter (DIT) that transmits S/PDIF data from 7 kHz to 216 kHz, up to 24-bit audio data. The first 48 bits of the channel status buffer are programmable. The source for the DIT is selectable from the built-in routing function of the PCM9211 as well as the dedicated inputs assigned to the MPIOs.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Data Mute Function The PCM9211 has the ability to mute the audio data on its DIT output. This option is set using Register 62h/TXDMUT. During a mute state (TXDMUT = '1'), the biphase stream continues to flow, but all audio data are zeroed. The channel status data and validity flag are not zeroed. Mute is done at the LRCK edge for both L-ch and R-ch data at the same time.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com MPIO Description Overview The PCM9211 offers significant flexibility through its MPIO pins. Depending on the system partitioning of the specific end product, the pins can be reconfigured to offer various I/Os that complement the design. There are 14 flexible pins: 12 are Input/Output pins, and two pins that are output only. The 12 multi-purpose I/O (MPIO) pins are grouped into three banks, each with four pins: MPIO_A, MPIO_B, and MPIO_C.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Muting Main Out and AUXOUT is done using Register 6Ah. Hi-Z control for Main Out is set with Register 6Dh. Assignable Signals to MPO Pins Both MPO pins have the same function.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Table 13. MPIO Group B (Pin: MPIO_B0 – MPIO_B3) MPBSEL[2:0] DIRECTION MPIO GROUP B FUNCTION 000 IN 001 OUT AUXIN2, ASCKI2/ABCKI2/ALRCKI2/ADIN2 (default) AUXOUT, ASCKO/ABCKO/ALRCKO/ADOUT 010 OUT Sampling frequency calculated result output, SFSOUT[3:0] 011 IN/OUT DIR Flags Output or GPIO 100 OUT 101 IN/OUT DIR BCUV_Output (BFRAME/COUT/UOUT/VOUT) 110 N/A Reserved 111 N/A Reserved External slave ADC input (EASCKO/EABCKO/EALRCKO/EADIN) Table 14.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Table 15. MPO0 Pin MPO0SEL[3:0] DIRECTION MPO0 FUNCTION 0000 OUT Hi-Z 0001 OUT GPO0, Output data = Logic high level 0010 OUT GPO0, Output data = Logic low level 0011 OUT VOUT 0100 OUT INT0 0101 OUT INT1 0110 OUT CLKST 0111 OUT EMPH 1000 OUT BPSYNC 1001 OUT DTSCD 1010 OUT PARITY 1011 OUT LOCK 1100 OUT XMCKO 1101 OUT TXOUT (default) 1110 OUT RECOUT0 1111 OUT RECOUT1 Table 16.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com MPIO Description Description for Signal Name Assigned to MPIO Table 17 through Table 25 list the details of where each of the internal PCM9211 signals can be routed to. For instance, DIR LOCK can be output to any of the MPIO and MPO pins, while SBCK (Secondary Clock Output) can only be brought out through MPIO_A0. Table 17.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Table 23.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Table 24. GPIO (General-Purpose Input/Output) (continued) SIGNAL NAME MPIO GROUP / PIN DESCRIPTION GPOC0 MPIO_C0 General-purpose output GPOC1 MPIO_C1 General-purpose output GPOC2 MPIO_C2 General-purpose output GPOC3 MPIO_C3 General-purpose output Table 25.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Default Routing Function (After RESET) The default routing paths are shown in Figure 32. MPIO_A0-A3 are selected by CLKST, VOUT, XMCKO, and INT0. Note that by default, MPIO_A0-A3 pins are Hi-Z as set by Registers MPA0HZ, MPA1HZ, MPA2HZ, and MPA3HZ.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Multi-Channel PCM Routing Function Overview The PCM9211 has a multi-channel PCM routing function (maximum of eight channels) that can route multi-channel PCM signals easily. This function is enabled by using all the MPIOs. MPIO_A and MPIO_C are assigned as multi-channel PCM input ports and clock transition outputs (CLKST). MPIO_B and the Main audio port are assigned as multi-channel PCM output ports.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Output Source Selection The output source for Multi-Channel PCM Output (the Main output port and MPIO_B) is selected by a register. Table 29 describes the relationship between the output source and the register (MCHRSRC) setting. Table 29.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Typical Register Settings Table 31 and Table 32 show the typical register settings for DSD format. Table 31. DSD Inputs From MPIO_Cx Ports REGISTER SETTINGS DESCRIPTIONS 34h = CFh RXSEL = TXOUT 61h = 14h TXDSD = Enable 6Bh = 14h MOSSRC = DIR MOPSRC = AUXIN1 Table 32.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Figure 35 shows a block diagram of DSD Input Mode (this illustration includes an example of DSD input = MPIO_Cx pins).
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Serial Control Mode The PCM9211 supports two types of control interface, which are set using the MODE pin (pin 27), as defined in Table 33. Table 33. Mode Control Interface Types MODE MODE CONTROL INTERFACE Tied to DGND Two-wire (I2C) serial control Tied to VDD Four-wire (SPI) serial control The input state of the MODE pin is only sampled during a power-on reset or external reset event. Therefore, any change after device power on or external reset is ignored.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register Write Operation Figure 37 shows the functional timing diagram for a single write operation on the serial control port. MS is held at '1' until a register must be written. To start the register write cycle, MS should be set to '0'. 16 clocks are then provided on MC, corresponding to the 16 bits of the control data word on MDI. After the 16th clock cycle has been completed, MS is set to '1' to latch the data into the indexed mode control register.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Timing Requirements Figure 39 shows a detailed timing diagram for the four-wire serial control interface. These timing parameters are critical for proper control port operation. t MHH MS 1.4 V t MCH tM S S t MCL t MS H MC 1.4 V t MCY t MDS MSB (R/W) MDI t MDH LSB (D0) ADR0 t MD D Hi - Z MDO SYMBOL tMCY tMCL tMCH tMHH tMSS tMSH tMDH tMDS tMDD tMDR t M DD MSB (D7) 1.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Packet Protocol A master device must control the packet protocol, which consists of a start condition, slave address with read/write bit, data if a write procedure is desired, or an acknowledgment if read and stop conditions exist. The PCM9211 supports both slave receiver and transmitter functions. Details of the DATA pulse for both write and read operations are described in Figure 40.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Timing Diagram Figure 43 shows the detailed timing diagram for SCL and SDA.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 APPLICATION INFORMATION TYPICAL CIRCUIT CONNECTION Figure 44 illustrates a typical circuit connection. +5V 0V +3.3V 0V C7 C8 Analog Input 48 47 46 45 44 43 42 41 40 39 38 37 VINR VINL VCCAD AGNDAD VCOM FILT VCC AGND XTO XTI GNDRX RXIN0 C10 C12 VDDRX 36 ERROR/ INT0 +3.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com APPLICATION EXAMPLE FOR ANALOG INPUT Figure 45 shows an example of VCOM biased buffering for 2-VRMS input with overvoltage protection. R2 C2 +V C1 +5V R1 Input R3 Output -V VCOM C3 0V Example of C and R values with gain (G) and corner frequency (fC): R1 = 20 kΩ R2 = 10 kΩ R3 = 1 kΩ C1 = 10 mF C2 = 330 pF C3 = 0.1 mF G = 0.5 fC = 48 kHz Figure 45.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 REGISTER INFORMATION Table 35.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Table 35.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 REGISTER DESCRIPTIONS NOTE Memo boxes are provided to aid in development. Record your register settings below for future reference.
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PCM9211 SBAS495 – JUNE 2010 www.ti.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 23h, DIR Initial Settings 3/3 (Address: 23h, Write and Read) DATA Reg Name Default Value Memo B7 RSV 0 B6 RSV 0 B5 XTIWT1 0 B4 XTIWT0 0 B3 PRTPRO1 0 B2 PRTPRO0 1 B1 ERRWT1 0 B0 ERRWT0 0 XTIWT[1:0]: Crystal OSC, Oscillation Start-up Wait Time Setting 00: 25 ms 01: 50 ms 10: 100 ms 11: 200 ms XTIWT is counted by the PLL generated clock. These are the resulting values when the PLL is running with a free-run clock because of no S/PDIF input.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 25h, ERROR Cause Setting (Address: 25h, Write and Read) DATA Reg Name Default Value Memo B7 RSV 0 B6 RSV 0 B5 EFSCHG 0 B4 EFSLMT 0 B3 ENPCM 0 B2 EVALID 0 B1 EPARITY 0 B0 EUNLOCK 1 The following ERROR Cause Setting registers are independent of the AUTO Source Selector Cause Setting Register (Register 26h).
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Register 26h, AUTO Source Selector Cause Setting (Address: 26h, Write and Read) DATA Reg Name Default Value Memo B7 ACKSL 0 B6 AERROR 0 B5 RSV 0 B4 AFSLMT 0 B3 ANPCM 0 B2 AVALID 0 B1 RSV 0 B0 AUNLOCK 1 The AUTO source selector is an automatic selector that outputs DIR or ADC output based on the following register settings. The following AUTO Source Selector Cause Setting registers are independent of the ERROR Cause Setting Register (Register 25h).
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 27h, DIR Acceptable fS Range Setting and Mask (Address: 27h, Write and Read) DATA Reg Name Default Value Memo B7 MSK128 0 B6 MSK64 0 B5 RSV 0 B4 NOMLMT 0 B3 HILMT1 0 B2 HILMT0 0 B1 LOLMT1 0 B0 LOLMT0 0 MSK128: Mask for fS = 128 kHz 0: No mask (default) 1: Mask PCM9211 does not receive 128-kHz sampling frequency. This register setting is effective with NOMLMT = '1'.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Register 2Ah, INT0 Output Cause Mask Setting (Address: 2Ah, Write and Read) DATA Reg Name Default Value Memo B7 MERROR0 1 B6 MNPCM0 1 B5 MEMPHF0 1 B4 MDTSCD0 1 B3 MCSRNW0 1 B2 MPCRNW0 1 B1 MFSCHG0 1 B0 RSV 1 MERROR0: ERROR Port Output Status 0: Not masked 1: Masked (default) MNPCM0: NPCM Port Output Status 0: Not masked 1: Masked (default) This register setting follows the register setting of non-PCM data identification.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 2Bh, INT1 Output Cause Mask Setting (Address: 2Bh, Write and Read) DATA Reg Name Default Value Memo B7 MERROR1 1 B6 MNPCM1 1 B5 MEMPHF1 1 B4 MDTSCD1 1 B3 MCSRNW1 1 B2 MPCRNW1 1 B1 MFSCHG1 1 B0 MADLVL1 1 MERROR1: ERROR Port Output Status 0: Not masked 1: Masked (default) MNPCM1: NPCM Port Output Status 0: Not masked 1: Masked (default) This register setting follows the register setting of non-PCM data identification.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Register 2Ch, INT0 Output Register (Address: 2Ch, Read-Only) DATA Reg Name Default Value Memo B7 OERROR0 N/A B6 ONPCM0 N/A B5 OEMPHF0 N/A B4 ODTSCD0 N/A B3 OCSRNW0 N/A B2 OPCRNW0 N/A B1 OFSCHG0 N/A B0 RSV 0 OERROR0: ERROR Port Output Status 0: No ERROR 1: Detect ERROR This register setting follows the register setting of the ERROR factor.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 2Dh, INT1 Output Register (Address: 2Dh, Read-Only) DATA Reg Name Default Value Memo B7 OERROR1 N/A B6 ONPCM1 N/A B5 OEMPHF1 N/A B4 ODTSCD1 N/A B3 OCSRNW1 N/A B2 OPCRNW1 N/A B1 OFSCHG1 N/A B0 OADLVL1 N/A OERROR1: ERROR Port Output Status 0: No ERROR 1: Detect ERROR This register setting follows the register setting of the ERROR factor.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 30h, DIR Recovered System Clock (SCK) Ratio Setting (Address: 30h, Write and Read) DATA Reg Name Default Value Memo B7 RSV 0 B6 RSV 0 B5 RSV 0 B4 PSCKAUTO 0 B3 RSV 0 B2 PSCK2 0 B1 PSCK1 1 B0 PSCK0 0 PSCKAUTO: PLL SCK Dividing Ratio Automatic Control Setting 0: Disable (default) 1: Enable This register is used to set the PLL SCK dividing ratio automatic control function. SCK setting is automatically set depending on the input sampling frequency.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Register 31h, XTI Source, Clock (SCK/BCK/LRCK) Frequency Setting (Address: 31h, Write and Read) DATA Reg Name Default Value Memo B7 RSV 0 B6 RSV 0 B5 XSCK1 0 B4 XSCK0 1 B3 XBCK1 1 B2 XBCK0 0 B1 XLRCK1 1 B0 XLRCK0 0 XSCK[1:0]: XTI Clock Source Frequency Setting 00: XTI/1 (24.576 MHz) 01: XTI/2 (12.288 MHz) (default) 10: XTI/4 (6.144 MHz) 11: XTI/8 (3.072 MHz) XBCK[1:0]: XTI Clock Source BCK Frequency Setting 00: XTI/2 (12.288 MHz) 01: XTI/4 (6.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Register 33h, XTI Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting (Address: 33h, Write and Read) DATA Reg Name Default Value Memo B7 RSV 0 B6 XSBCK2 0 B5 XSBCK1 1 B4 XSBCK0 0 B3 RSV 0 B2 XSLRCK2 0 B1 XSLRCK1 1 B0 XSLRCK0 0 XSBCK[2:0]: XTI Clock Source, Secondary BCK (SBCK) Frequency Setting 000: XTI/2 (12.288 MHz) 001: XTI/4 (6.144 MHz) 010: XTI/8 (3.072 MHz) (default) 011: XTI/16 (1.536 MHz) 100: XTI/32 (0.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 46h, ADC L-Ch, Digital ATT Control (Address: 46h, Write and Read) DATA Reg Name Default Value Memo B7 ADATTL7 1 B6 ADATTL6 1 B5 ADATTL5 0 B4 ADATTL4 1 B3 ADATTL3 0 B2 ADATTL2 1 B1 ADATTL1 1 B0 ADATTL0 1 B1 ADATTR1 1 B0 ADATTR0 1 ADATTL[7:0]: ADC L-Ch, Digital ATT Setting 1111 1111: +20.0 dB 1111 1110: +19.5 dB 1101 0111: 0 dB (default) 1101 0110: –0.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Register 48h, ADC Function Control 2/3 (Address: 48h, Write and Read) DATA Reg Name Default Value Memo B7 RSV 0 B6 ADIFMD2 0 B5 ADIFMD1 0 B4 ADIFMD0 0 B3 RSV 0 B2 RSV 0 B1 ADFMT1 0 B0 ADFMT0 0 ADIFMD[2:0]: ADC Interface Mode Setting 000: Slave mode (default) 001: Reserved 010: Master mode, 512fS 011: Reserved 100: Master mode, 256fS 101: Reserved 110: Reserved 111: Reserved Master mode settings are available only in ADC standalone mode (MPCSEL[2:0] = '001').
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 49h, ADC Function Control 3/3 (Address: 49h, Write and Read) DATA Reg Name Default Value Memo B7 RSV 0 B6 RSV 0 B5 RSV 0 B4 ADZCDD 0 B3 ADBYP 0 B2 ADPHSE 0 B1 ADMUTR 0 B0 ADMUTL 0 ADZCDD: Zero-Crossing Detection Disable for Digital Attenuation 0: Enable (default) 1: Disable.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Register 6Ah, Main Output and AUXOUT Port Control (Address: 6Ah, Write and Read) DATA Reg Name Default Value Memo B7 AOMUTAS 0 B6 MOMUTAS 0 B5 RSV 0 B4 RSV 0 B3 AOLRMTEN 0 B2 AODMUT 0 B1 MOLRMTEN 0 B0 MODMUT 0 AOMUTAS: AUX Output Port, Mute Synchronization Select (MPIO_B2 and MPIO_B3) 0: AODMUT works with synchronization with LRCK edge.
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PCM9211 www.ti.com SBAS495 – JUNE 2010 Register 6Dh, MPIO_B and Main Output Port Hi-Z Control (Address: 6Dh, Write and Read) DATA Reg Name Default Value Memo B7 MPB3HZ 0 B6 MPB2HZ 0 B5 MPB1HZ 0 B4 MPB0HZ 0 B3 SCKOHZ 0 B2 BCKHZ 0 B1 LRCKHZ 0 B0 DOUTHZ 0 MPB3HZ: MPIO_B3, Hi-Z Control 0: Defined by Group Function Assign register, 6Fh/MPBSEL. (default) 1: Hi-Z MPB2HZ: MPIO_B2, Hi-Z Control 0: Defined by Group Function Assign register, 6Fh/MPBSEL.
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PCM9211 SBAS495 – JUNE 2010 www.ti.com Register 6Eh, MPIO_C and MPIO_A Hi-Z Control (Address: 6Eh, Write and Read) DATA Reg Name Default Value Memo B7 MPC3HZ 0 B6 MPC2HZ 0 B5 MPC1HZ 0 B4 MPC0HZ 0 B3 MPA3HZ 1 B2 MPA2HZ 1 B1 MPA1HZ 1 B0 MPA0HZ 1 MPC3HZ: MPIO_C3, Hi-Z Control 0: Defined by Group Function Assign register, 6Fh/MPCSEL. (default) 1: Hi-Z MPC2HZ: MPIO_C2, Hi-Z Control 0: Defined by Group Function Assign register, 6Fh/MPCSEL.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device PCM9211PTR Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.9 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM9211PTR LQFP PT 48 1000 367.0 367.0 38.
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MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.