Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Programmable gain TSSOP 20

PGA112

PGA113

PGA117

PGA116

FEATURES APPLICATIONS

DESCRIPTION

10kW

ADC

G=1

Output

Stage

SPI

Interface

SCLK

DIO

OUT

GND

REF

MSP430

Microcontroller

+3V

+5V

REF

PGA112

PGA113

V /CH0

CAL

CH1

CAL3

CAL4

CAL1

CAL2

0.1V

CAL

0.9V

CAL

10kW

80kW

MUX

CAL2/3

0.1 F

BYPASS

0.1 F

BYPASS

0.1 F

BYPASS

PGA112

, ,

PGA113

PGA116

PGA117

www.ti.com

............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008

Zer ø -Drift

PROGRAMMABLE GAIN AMPLIFIER with MUX

• Remote e-Meter Reading

• Rail-to-Rail Input/Output

• Automatic Gain Control

• Offset: 25 µ V (typ), 100 µ V (max)

• Portable Data Acquisition

• Zer ø Drift: 0.35 µ V/ ° C (typ), 1.2 µ V/ ° C (max)

• PC-Based Signal Acquisition Systems

• Low Noise: 12nV/ √ Hz

• Test and Measurement

• Input Offset Current: ± 5nA max (+25 ° C)

• Programmable Logic Controllers

• Gain Error: 0.1% max (G ≤ 32),

• Battery-Powered Instruments

0.3% max (G > 32)

• Handheld Test Equipment

• Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128

(PGA112, PGA116)

• Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200

The PGA112 and PGA113 (binary/scope gains) offer

(PGA113, PGA117)

two analog inputs, a three-pin SPI interface, and

• Gain Switching Time: 200ns

software shutdown in an MSOP-10 package. The

• Two Channel MUX: PGA112, PGA113

PGA116 and PGA117 (binary/scope gains) offer 10

10 Channel MUX: PGA116, PGA117

analog inputs, a four-pin SPI interface with

daisy-chain capability, and hardware and software

• Four Internal Calibration Channels

shutdown in a TSSOP-20 package.

• Amplifier Optimized for Driving CDAC ADCs

All versions provide internal calibration channels for

• Output Swing: 50mV to Supply Rails

system-level calibration. The channels are tied to

• AV

and DV

for Mixed Voltage Systems

GND, 0.9V

CAL

, 0.1V

CAL

, and V

REF

, respectively. V

CAL

• I

= 1.1mA (typ)

an external voltage connected to Channel 0, is used

as the system calibration reference. Binary gains are:

• Software/Hardware Shutdown: I

≤ 4 µ A (typ)

1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2,

• Temperature Range: – 40 ° C to +125 ° C

5, 10, 20, 50, 100, and 200.

• SPI™ Interface (10MHz) with Daisy-Chain

Capability

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 SPI is a trademark of Motorola.

3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (48 pages)

PAGE 1
PG A1 16 PGA112, PGA113 PGA116, PGA117 PG A1 17 PG A1 12 PG A1 13 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 Zerø-Drift PROGRAMMABLE GAIN AMPLIFIER with MUX FEATURES APPLICATIONS • • • • • • • • • • • • • • 1 23 • • • • • • • • • • • • Rail-to-Rail Input/Output Offset: 25µV (typ), 100µV (max) Zerø Drift: 0.35µV/°C (typ), 1.
PAGE 2
PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS: VS = AVDD = DVDD = +5V Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com ELECTRICAL CHARACTERISTICS: VS = AVDD = DVDD = +5V (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ELECTRICAL CHARACTERISTICS: VS = AVDD = DVDD = +5V (continued) Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
PAGE 6
PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com SPI TIMING: VS = AVDD = DVDD = +2.2V to +5V Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, RL = 10kΩ//CL = 100pF connected to DVDD/2, and VREF = GND, unless otherwise noted.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 SPI TIMING DIAGRAMS tCSH CS tCSSC tSCCS tLO tCS1 tCS0 tHI SCLK 1/fSCLK tSU tHD DIN tSOZ tDO Hi-Z Hi-Z DOUT Figure 2. SPI Mode 0, 0 tCSH CS tCSSC tSCCS tHI tCS1 tCS0 tLO SCLK 1/fSCLK tSU tHD DIN tDO tSOZ Hi-Z Hi-Z DOUT Figure 3.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com PIN CONFIGURATIONS MSOP-10 DGS PACKAGE (TOP VIEW) AVDD 1 CH1 2 PGA112 PGA113 10 DVDD 9 CS 8 DIO VCAL/CH0 3 VREF 4 7 SCLK VOUT 5 6 GND PGA112, PGA113 TERMINAL FUNCTIONS MSOP PACKAGE PIN # NAME DESCRIPTION 1 AVDD Analog supply voltage (+2.2V to +5.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com TYPICAL APPLICATION CIRCUITS +3V +5V CBYPASS 0.1mF CBYPASS 0.1mF AVDD CBYPASS 0.1mF DVDD 1 10 MSP430 Microcontroller PGA112 PGA113 3 VCAL/CH0 MUX 2 CH1 Output Stage 5 VOUT 7 SCLK ADC CAL1 10kW 0.9VCAL 0.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted. OFFSET VOLTAGE OFFSET VOLTAGE VCM = 4.5V -325.0 -292.5 -260.0 -227.5 -195.0 -162.5 -130.0 -97.5 -65.0 -32.5 0 32.5 65.0 97.5 130.0 162.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted. INPUT OFFSET VOLTAGE vs INPUT VOLTAGE PGA112/PGA116 NONLINEARITY 0.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted. GAIN ERROR DRIFT (–40°C to +125°C) GAIN ERROR DRIFT (–40°C to +125°C) 1 < G £ 32 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted. 0.1Hz TO 10Hz NOISE 0.1Hz TO 10Hz NOISE 100nV/div VS = 5V 250nV/div VS = 2.2V 2.5s/div 2.5s/div Figure 24. Figure 25.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted. PGA113, PGA117 THD + NOISE vs FREQUENCY (VOUT = 4VPP) QUIESCENT CURRENT vs TEMPERATURE 1 0.8 G = 100 G = 200 G = 50 0.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted. PGA112, PGA116 OUTPUT VOLTAGE SWING vs FREQUENCY PGA112, PGA116 OUTPUT VOLTAGE SWING vs FREQUENCY 2.5 2.5 AVDD = DVDD = 2.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
PAGE 18
PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
PAGE 19
PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = DVDD = 5V, RL = 10kΩ connected to DVDD/2, VREF = GND, and CL = 100pF, unless otherwise noted.
PAGE 20
PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com SERIAL INTERFACE INFORMATION SPI Mode 0, 0 (CPOL = 0, CPHA = 0) CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK DIN DOUT SPI Mode 1, 1 (CPOL = 1, CPHA = 1) CS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK DIN DOUT Figure 58.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 On the PGA112/PGA113, there are digital output and digital input gates both internally connected to the DIO pin. DIN is an input-only gate and DOUT is a digital output that can give a 3-state output.
PAGE 22
PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com The maximum SCLK frequency that can be used in daisy-chain operation is directly related to SCLK rise/fall times, DIN setup time, and DOUT propagation delay.
PAGE 23
Copyright © 2008, Texas Instruments Incorporated DIO Pin DIO Pin DIO Pin DIO Pin Product Folder Link(s): PGA112 PGA113 PGA116 PGA117 DOUT DIN SCLK CS DOUT DIN SCLK CS DOUT DIN SCLK CS DOUT DIN SCLK CS 0 D15 1 D15 0 1 D15 1 D15 1 1 D14 2 D14 1 2 D14 2 D14 2 D13 1 3 D13 1 3 D13 3 D13 3 D12 0 4 D12 0 4 D12 4 D12 4 D11 1 5 D11 1 5 D11 5 D11 5 Hi-Z D10 0 6 Hi-Z D10 0 6 Hi-Z D10 6 Hi-Z D10 6 D8 8 D7 9 D6 10 D8 8 D7 9 D6
PAGE 24
Submit Documentation Feedback Product Folder Link(s): PGA112 PGA113 PGA116 PGA117 DOUT1 DIN2 DOUT DIN1 SCLK CS DOUT1 DIN2 DOUT DIN1 SCLK CS D15 1 D15 1 D14 2 D14 2 D11 5 D10 6 D9 7 D7 9 Command U2 D8 8 D12 4 D11 5 D10 6 D8 8 Command U2 D9 7 D7 9 DOUT Hi-Z Pulled Low by DIN Weak Pull-Down D12 4 DOUT Hi-Z Pulled Low by DIN Weak Pull-Down D13 3 D13 3 D6 10 D6 10 D5 11 D5 11 MSP430 D4 12 D4 12 CS SCLK DOUT DIN D3 13 D3 13 D2 14 D2 14 DO
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Copyright © 2008, Texas Instruments Incorporated CS Product Folder Link(s): PGA112 PGA113 PGA116 PGA117 0 0 DOUT2 DIN 0 1 DOUT1 DIN2 SCLK DOUT1 DIN2 DOUT DIN1 SCLK CS 1 1 2 0 0 2 1 3 1 5 0 6 1 7 0 9 Command U2 0 8 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 G3 G3 9 DOUT Hi-Z Pulled Low by DIN Weak Pull-Down 1 4 0 10 G2 G2 10 0 11 G1 G1 11 MSP430 0 G0 12 13 CH3 0 13 CH3 Data Byte U2 G0 Data Byte U1 12 CS SCLK DOUT DIN 14 CH2 CH2 0 14
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Submit Documentation Feedback CS Product Folder Link(s): PGA112 PGA113 PGA116 PGA117 0 0 DOUT2 DIN 0 1 DOUT1 DIN2 SCLK DOUT1 DIN2 DOUT DIN1 SCLK CS 17 1 2 0 0 18 1 3 1 5 0 6 1 7 0 9 Command U2 0 8 0 0 19 0 0 20 0 0 21 0 0 22 0 0 23 0 0 24 G3 G3 25 DOUT Hi-Z Pulled Low by DIN Weak Pull-Down 1 4 0 10 G2 G2 26 0 11 G1 G1 27 MSP430 0 G0 28 29 CH3 0 13 CH3 Data Byte U2 G0 Data Byte U1 12 CS SCLK DOUT DIN 30 CH2 CH2 0 14 15 31
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 SPI COMMANDS Table 3.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com Table 6.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 APPLICATION INFORMATION The PGA112/PGA113 and PGA116/PGA117 are single-ended input, single-supply, programmable gain amplifiers (PGAs) with an input multiplexer. Multiplexer channel selection and gain selection are done through a standard SPI interface.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com 50 CH0 AVDD = 5V Input Offset Voltage (mV) 40 CH1 PGA112 PGA113 MUX VOUT RI 30 VIN0 VIN1 VREF RF 20 + 10 G=1 VS/2 - 0 -10 Figure 72.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 OP AMP: FREQUENCY RESPONSE VERSUS GAIN Table 8 documents how small-signal bandwidth and slew rate change correspond to changes in PGA gain.
PAGE 32
PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com +3V +3V CBYPASS 0.1mF CBYPASS 0.1mF CBYPASS 0.1mF AVDD DVDD REF3225 PGA112 PGA113 VCAL/CH0 MUX VOUT Output Stage CH1 2.5V ADC Ref ADC CAL1 10kW RF G=1 0.9VCAL 0.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 +3V +3V CBYPASS 0.1mF AVDD CBYPASS 0.1mF CBYPASS 0.1mF DVDD PGA112 PGA113 VCAL/CH0 ADC Ref MUX CAL1 10kW MSP430 Microcontroller CAL2 0.1VCAL CAL3 80kW ADC RF G=1 0.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com SYSTEM CALIBRATION USING THE PGA Analog-to-digital converters (ADCs) contain two major errors that can be easily removed by calibration at a system level. These errors are gain error and offset error, as shown in Figure 75.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 The 12-bit ADC example in Figure 76 illustrates the technique for calibrating an ADC using a 10%VREF_ADC and 90%VREF_ADC reading where VREF_ADC is the ADC reference voltage. Note that the 10%VREF reading also contains a gain error because it is not a VIN = 0 calibration point.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com APPLICATIONS: GENERAL-PURPOSE INPUT SCALING Figure 77 is an example application that demonstrates the flexibility of the PGA for general-purpose input scaling. VIN0 is a ±100mV input that is ac-coupled into CH0.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 Table 12. Bipolar to Single-Ended Input Scaling (1) (2) VREF_ADC (V) VIN1 (V) CH1 INPUT RA (kΩ) RX (Ω) RB (kΩ) 2.5 –5 0.047613 9.2 4.81k 10 0 1.247613 3.16 2.4k 10 13.5 5.76k 10 4.02 2.87k 10 37 7.87k 10 6.49 3.92k 10 24 965 10 9.2 4.81k 10 2.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com Bipolar Input to Single-Supply Scaling Note that this process assumes a symmetrical VIN1 and that symmetrical scaling is used for CH1 input minimum and maximum values. The following steps give the algorithm to compute resistor values for references not listed in Table 12.
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PGA112,, PGA113 PGA116, PGA117 www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 2. Signal trace routing. Keep VOUT and other low impedance traces away from MUX channel inputs that are high impedance. Poor signal routing can cause positive feedback, unwanted oscillations, or excessive overshoot and ringing on step-changing signals.
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PGA112,, PGA113 PGA116, PGA117 SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008 ............................................................................................................................................ www.ti.com POWER SUPPLIES At initial power-on, the state of the PGA is G = 1 and Channel 0 active. CAUTION: For most applications, set AVDD ≥ DVDD to prevent VOUT from driving current into AVDD and raising the voltage level of AVDD.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PGA112AIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 PGA112AIDGSR VSSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PGA112AIDGST VSSOP DGS 10 250 180.0 12.4 5.3 3.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PGA112AIDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 PGA112AIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0 PGA112AIDGST VSSOP DGS 10 250 195.0 200.0 45.0 PGA112AIDGST VSSOP DGS 10 250 366.0 364.0 50.0 PGA113AIDGSR VSSOP DGS 10 2500 370.0 355.0 55.0 PGA113AIDGST VSSOP DGS 10 250 195.0 200.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.