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SCANSTA101

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SNLS057J –MAY 2002–REVISED APRIL 2013

SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master

Check for Samples: SCANSTA101

FEATURES

DESCRIPTION

The SCANSTA101 is designed to function as a test

• Compatible with IEEE Std. 1149.1 (JTAG) Test

master for an IEEE 1149.1 boundary scan test

Access Port and Boundary Scan Architecture

system. It is suitable for use in embedded IEEE

• Supported by Texas Instruments' SCAN Ease

1149.1 applications and as a component in a stand-

(SCAN Embedded Application Software

alone boundary scan tester.

Enabler) Software Rev 2.0

The SCANSTA101 is an enhanced version of, and a

• Uses Generic, Asynchronous Processor

replacement for, the SCANPSC100. The

Interface; Compatible with a Wide Range of

SCANSTA101 supports the IEEE 1149.1 Test Access

Processors and Processor Clock (PCLK)

Port (TAP) standard and the IEEE 1532 standard for

Frequencies

in-system configuration of programmable devices.

• 16-Bit Data Interface (IP Scalable to 32-bit)

The SCANSTA101 improves test vector throughput

• 2k x 32 Bit Dual-Port Memory

and reduces software overhead in the system

processor. The SCANSTA101 presents a simple,

• Load-on-the-Fly (LotF) and Preloaded Vector

Operating Modes Supported

Texas Instruments provides C-language source code

• On-Board Sequencer Allows Multi-Vector

which can be included in the embedded system

Operations such as those Required to Load

software. The combination of the SCANSTA101 and

Data Into an FPGA

its support software comprises a simple API for

boundary scan operations.

• On-Board Compares Support Test Data In

(TDI) Validation Against Preloaded Expected

The interface from the SCANSTA101 to the system

Data

processor is implemented by reading and writing

registers, some of which map to locations in the

• 32-Bit Linear Feedback Shift Register (LFSR)

SCANSTA101 memory. Hardware handshaking and

at the Test Data In (TDI) Port for Signature

interrupt lines are provided as part of the processor

Compression

interface.

• State, Shift, and BIST Macros Allow

The SCANSTA101 is available as a stand-alone

Predetermined Test Mode Select (TMS)

device packaged in a 49-pin NFBGA package. It is

Sequences to be Utilized

also available as an IP macro for synthesis in

• Operates at 3.3 V Supply Voltages with 5 V

programmable logic devices.

Tolerant I/O

• Outputs Support Power-Down TRI-STATE

Mode.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 SCANSTA101 Low Voltage IEEE 1149.1 System Test Access (STA) Master Check for Samples: SCANSTA101 FEATURES DESCRIPTION • The SCANSTA101 is designed to function as a test master for an IEEE 1149.1 boundary scan test system. It is suitable for use in embedded IEEE 1149.1 applications and as a component in a standalone boundary scan tester. 1 2 • • • • • • • • • • • Compatible with IEEE Std. 1149.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com SCANSTA101 ARCHITECTURE Figure 1. SCANSTA101 STA Master and Interfaces Figure 1 shows a high level view of the SCANSTA101 STA Master and its interfaces. Table 1 provides a brief description of each of these interfaces. provides a brief description of the device pins and their functions. The device is composed of three interfaces around a dual-port memory.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 CONNECTION DIAGRAM Figure 2. NFBGA Package Pinout (Top View) PIN DESCRIPTIONS Pin Name No. Pins I/O VCC 4 N/A Power GND 4 N/A Ground D(15:0) 16 I/O Bidirectional Data Bus. Signals are bonded out for the packaged device. 16 I/O Bidirectional Data Bus. These signals are not available in the packaged device. A(4:0) 5 I Address Bus SCK 1 I The system clock that drives all internal timing.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name No. Pins I/O TDI 1 I Test Data In is the serial scan input to the SCANSTA101. TMS 1 I Test Mode Select. The Test Mode Select pin is a serial input used to accept control logic to the test & debug interface. TCK 1 I Test Clock Input for 1149.1 TRST 1 I Test Reset.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) −0.5V to +4.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VO = −0.5V −20 mA DC Input Voltage (VI) −0.5V to +4.0V DC Output Diode Current (IOK) DC Output Voltage (VO) −0.5V to +4.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com DC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min VCC = 0.0V Max Units 5.0 μA IOFF Power Off Leakage Current All pins except TDI, TMS, TRST, and TDI_SM ICC Maximum Quiescent Supply Current 250 μA ICCmax Maximum Supply Current All inputs low 1.2 mA ICCT Maximum ICC/Input VIN = VCC − 0.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 AC ELECTRICAL CHARACTERISTICS/OPERATING REQUIREMENTS (continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified. CL = 50 pF, RL = 500Ω unless otherwise specified.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 Symbol www.ti.com Parameter Conditions Min Max Units tWL Reset Pulse Width TRST (L) 2.5 ns tREC Recovery Time TCK from TRST 2.0 ns fMAX Maximum Clock Frequency, TCK 25 MHz APPLICATIONS/PROGRAMMERS REFERENCE Table 2.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 Table 3.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com Table 6.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 Table 10. SCAN BRIDGE SUPPORT STRUCTURE Bit(s) Function 0x00 - 0x0F Levels of Scan Bridge support to be inserted in the scan chain 0x10 - 0x17 Hierarchical Level 0 Scan Bridge Address 0x18 - 0x1F Hierarchical Level 0 Scan Bridge LSP 0x20 - 0x27 Hierarchical Level 1 Scan Bridge Address 0x28 - 0x2F Hierarchical Level 1 Scan Bridge LSP ..x.. - ..x..
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com All the control for this block is provided by the PIC and MRD with the 16/32-bit mode enable coming from the Setup register. EDGE DETECTOR The PPI module can support either an asynchronous or synchronous processor interface. For an asynchronous interface, the circuit initially synchronizes STB and CE to the system clock, SCK, by pipelining these two signals through two flip-flop stages and then performing an edge detection on STB and CE.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 If an interrupt enable is set then an interrupt will be generated. If an interrupt occurs at the same time as the interrupt status is being read, then the interrupt will be set after the read is complete. All bits in the Interrupt Status register are cleared when the register is read. FLAG GENERATOR The FG takes in the TDI_SM or TDO_SM pointer values from the PPI address pointers, compares them and generates the appropriate flags.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 • • • • • • www.ti.com Structure (Sequencer/Vector/Macro/ScanBridge) Control Registers Count Generator Shifter (TDO_SM/TDI_SM/TMS_SM) Comparator Expected and Mask Registers Serial Scan Interface Controller (SSIC) and ScanBridge Controller The clock divider unit divides the system clock SCK based on the programmable divisor set in the clock divider to generate TCK_SM. The TCK_SM control unit gates TCK_SM if the TDO_SM buffer is empty.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 The SCANSTA101 memory is organized in big endian format. A memory write is accomplished by two consecutive writes to the same location. When embedded software loads the TDO_SM memory, the least significant 16 bits are written first and then the most significant 16 bits. Therefore, when the Sequencer or a Vector is initialized the SSIC can directly fetch and load the long word to the TDO_SM shifter without any modification. Figure 3.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com The 32-bit shift register at the bottom is used to shift in TDI_SM directly in normal mode or to shift in TMS_SM or TDO_SM in the loop-back mode. After each long word of 32 bits is shifted into this register, the contents of the register are transferred to the corresponding TDI memory location before the next shift operation. SHIFTER IMPLEMENTATION Shift register implementation is illustrated in Figure 6.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 COMPARATOR AND EXPECTED/MASK REGISTERS The One-Bit Comparator, when enabled, compares the TDI_SM input with expected data. When the compare feature is enabled (in preloaded vector mode only) the SSIC pre-fetches data into Expected and Mask registers from the address locations for the current vector being processed. The comparator will compare each bit on the TDI_SM input with the corresponding bit from the expected register.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com SERIAL SCAN INTERFACE CONTROLLER AND SCANBRIDGE CONTROLLER The Serial Scan Interface Controller (SSIC) remains in the Idle state until new data are written to the Start register. When this event occurs the following operations are performed: 1.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 Structure Control registers. 6. If the Pre-shift TCK_SM Count is not zero, then enable TCK_SM and drive TMS_SM using the first seven bits of the macro until the Pre-shift TCK_SM Count is zero. During pre-shift, TDO_SM will be driven with its previous value. 7. If the macro type is State then, (a) If the Macro Structure Bit 7 is enabled, set TMS_SM to the bit 7 value of the macro structure and drive TDO_SM with its previous value.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com (c) Decrement the vector repeat count and return to Step 3E if the Compare or Mask/ Compare is not enabled. 12. If the Vector is being used return to the Idle state. MODE REGISTER WRITE TO VECTOR/SEQUENCER START Figure 8 shows the timing from the processor write to the start of vector processing. Figure 9 shows the timing from the processor write to the start of sequencer processing.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 WRITING AND READING PARTIAL LONG WORDS Care should be taken when writing a partial long word to TDO_SM memory or reading a partial long word from TDI_SM memory. Since the TDO_SM shifter shifts out LSB first, the valid (meaningful) bits within a partial long word (i.e., long word containing less than 32 valid bits to be shifted to the scan chain) must be stored and written into the memory as the least significant bits.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com HARDWARE INTERFACE DETAILS Table 13. System Interface Signal Description Signal Name No. of Bits Pin Type Driver Type Freq. MHz Description SCK 1 I LVTTL 66 System Clock: This is the main clock signal to the SCANSTA101. SCK is used to clock all internal circuitry RST 1 I,H LVTTL N/A Hardware Reset signal (with hysteresis (H)): This is the SCANSTA101 asynchronous reset signal.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 Figure 12. PPI Write Cycle Timing Diagram Figure 13. PPI Read Cycle Timing Diagram Figure 14.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com Figure 15. SSI Timing Diagram with Clock Divider set to 8 Table 16. SCANSTA101 1149.1 Signal Descriptions No. of Bits Pin Type Driver Type Freq.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 RESET STRATEGY The incoming external hardware reset (RST) will be synchronized to the incoming clock (SCK) and is combined with the soft reset to generate a synchronized internal reset (SYS_RST_N). During operation, the chip can be reset by writing a '1' to the Reset bit in the Setup register.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com Table 18.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 Table 19.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com Table 20.
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SCANSTA101 www.ti.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com Table 23. TDI_SM LFSR Exponent Register (EXPR) ($07) Bit(s) Type Address Offset Reset Value 15:3 RO Reserved Field 0 0000h 2:0 RW LFSR 0 000b LFSR Exponent<2:0> LFSR exponent. Binary encoding for the selection between three polynomials. '000' No polynomial selected '001' Polynomial 1: X32 + X7 + X5 + X3 + X2 + X + 1 '010' Polynomial 2: X32 + X28 + X27 + X + 1 '011' Polynomial 3: X32 + X7 + X6 + X2 + 1 Table 24.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 Table 30. Header/Trailer Index Register (HTINDEXR) ($13) (1) (2) Bit(s) Type 15:0 RW Field Address Offset Reset Value Reset Source 0 0000h SYS_RST Header/Trailer Index Header/Trailer Index<15:0> sets the Header/Trailer address memory pointer. Address memory pointer must be on a long word boundary. Table 31.
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SCANSTA101 SNLS057J – MAY 2002 – REVISED APRIL 2013 www.ti.com Table 36.
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SCANSTA101 www.ti.com SNLS057J – MAY 2002 – REVISED APRIL 2013 REVISION HISTORY April, 2013 – Changed layout of National Data Sheet to TI format. January, 2010 – Applications information updates and clarification. No specification changes.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SCANSTA101SMX Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant NFBGA NZA 49 2000 330.0 16.4 7.3 7.3 2.1 12.0 16.0 Q1 SCANSTA101SMX/NOPB NFBGA NZA 49 2000 330.0 16.4 7.3 7.3 2.1 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SCANSTA101SMX NFBGA NZA 49 2000 367.0 367.0 38.0 SCANSTA101SMX/NOPB NFBGA NZA 49 2000 367.0 367.0 38.
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MECHANICAL DATA NZA0049A SLC49A (Rev B) www.ti.
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