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SCANSTA111

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SNLS060K –AUGUST 2001–REVISED APRIL 2013

SCANSTA111 Enhanced SCAN Bridge

Multidrop Addressable IEEE 1149.1 (JTAG) Port

Check for Samples: SCANSTA111

FEATURES

DESCRIPTION

The SCANSTA111 extends the IEEE Std. 1149.1 test

• True IEEE 1149.1 Hierarchical and Multidrop

bus into a multidrop test bus environment. The

Addressable Capability

advantage of a multidrop approach over a single

• The 7 Slot Inputs Support Up to 121 Unique

serial scan chain is improved test throughput and the

Addresses, an Interrogation Address,

ability to remove a board from the system and retain

Broadcast Address, and 4 Multi-Cast Group

test access to the remaining modules. Each

Addresses (Address 000000 is Reserved)

SCANSTA111 supports up to 3 local IEEE 1149.1

scan rings which can be accessed individually or

• 3 IEEE 1149.1-Compatible Configurable Local

combined serially. Addressing is accomplished by

Scan Ports

loading the instruction register with a value matching

• Mode Register

Allows Local TAPs to be

that of the Slot inputs. Backplane and inter-board

Bypassed, Selected for Insertion Into the Scan

testing can easily be accomplished by parking the

Chain Individually, or Serially in Groups of

local TAP Controllers in one of the stable TAP

Two or Three

Controller states via a Park instruction. The 32-bit

TCK counter enables built in self test operations to be

• Transparent Mode can be Enabled with a

performed on one port while other scan chains are

Single Instruction to Conveniently Buffer the

simultaneously tested.

Backplane IEEE 1149.1 Pins to those on a

Single Local Scan Port

• LSP ACTIVE Outputs Provide Local Port

Enable Signals for Analog Busses Supporting

IEEE 1149.4.

• General Purpose Local Port Pass-Through Bits

are Useful for Delivering Write Pulses for

FPGA Programming or Monitoring Device

Status.

• Known Power-Up State

• TRST on All Local Scan Ports

• 32-Bit TCK Counter

• 16-Bit LFSR Signature Compactor

• Local TAPs can become TRI-STATE via the OE

Input to Allow an Alternate Test Master to Take

Control of the Local TAPs (LSP

0-2

Have a TRI-

STATE Notification Output)

• 3.0-3.6V V

Supply Operation

• Power-Off High Impedance Inputs and Outputs

• Supports Live Insertion/Withdrawal

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port Check for Samples: SCANSTA111 FEATURES DESCRIPTION • The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com CONNECTION DIAGRAM Table 1. Glossary LFSR Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test data. LSP Local Scan Port. A four signal port that drives a local (i.e. non-backplane) scan chain. (e.g., TCK0, TMS0, TDO0, TDI0). Local Local is used to describe IEEE Std. 1149.1 compliant scan rings and the SCANSTA111 Test Access Port that drives them.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 ARCHITECTURE Figure 1 shows the basic architecture of the 'STA111. The device's major functional blocks are illustrated here. The TAP Controller, a 16-state state machine, is the central control for the device. The instruction register and various test data registers can be scanned to exercise the various functions of the 'STA111 (these registers behave as defined in IEEE Std. 1149.1).
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS No. Pins I/O VCC 3 N/A Power GND 3 N/A Ground TMSB 1 I BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the 'STA111. Also controls sequencing of the TAPs which are on the local scan chains. This input has a 25KΩ pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method).
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) No. Pins I/O LSP_ACTIVE(0-2) 3 O LOCAL ANALOG TEST BUS ENABLE: These analog pins serve as enable signals for analog busses supporting the IEEE 1149.4 Mixed-Signal Test Bus standard , or for backplane physical layer changes (therefore; TTL to LVDS). These outputs have 12mA of drive current. TRIST(0-2) 3 O LOCAL TRI-STATE NOTIFICATION OUTPUTS: This signal is high when the local scan ports are TRI-STATEd .
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com Figure 2. SCANSTA111 State Machines The 'STA111 contains three distinct but coupled state-machines (see Figure 2). The first of these is the TAPcontrol state-machine, which is used to drive the 'STA111's scan ports in conformance with the 1149.1 Standard. The second is the 'STA111-selection state-machine (Figure 3).
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 Figure 4. Local SCANSTA111 Port Configuration State Machine The 'STA111's scan port-configuration state-machine is used to control the insertion of local scan ports into the overall scan chain, or the isolation of local ports from the chain. From the perspective of a system's (single) scan controller, each 'STA111 presents only one scan chain to the master.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com Figure 5 illustrates how the 'STA111's state-machines interact. The 'STA111-selection state-machine enables or disables operation of the chip's three port-selection state-machines. In 'STA111s which are selected via Level-1 protocol (either as individual 'STA111s or as members of broadcast or multi-cast groups), Level-2 protocol commands can be used to park or unpark local scan ports.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 TESTER/SCANSTA111 INTERFACE An IEEE 1149.1 system tester sends instructions to a 'STA111 via that 'STA111's backplane scan-port. Following test logic reset, the 'STA111's selection state-machine is in the Wait-For-Address state. When the 'STA111's TAP controller is sequenced to the Shift-IR state, data shifted in through the TDIB input is shifted into the 'STA111's instruction register.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com LEVEL 1 PROTOCOL (ADDRESSING MODES) Table 3. SCANSTA111 Address Modes Address Type Hex Address Binary Address TDOB State Direct Address 00 to 39, 00000000 to 00111010 Normal IEEE Std. 1149.1 40 to 7F. 01000000 to 01111111 (80 to FF (1)) (10000000 to 11111111 (1)) Interrogation Address 3A 00111010 Force strong 0' or weak 1' as ones-complement address is shifted out.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 Figure 6. Direct Addressing: Device Address Loaded into Instruction Register Figure 7. Broadcast Addressing: Address Loaded into Instruction Register Figure 8.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com LEVEL 2 PROTOCOL Once the SCANSTA111 has been successfully addressed and selected, its internal registers may be accessed via Level-2 Protocol. Level-2 Protocol is compliant to IEEE Std. 1149.1 TAP protocol with one exception: if the 'STA111 is selected via the Broadcast or Multi-Cast address, TDOB is always TRI-STATED. (The TDOB buffer must be implemented this way to prevent bus contention.) Upon being selected, (i.e.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 Table 4.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com PARKRTI: This instruction causes all unparked LSPs to be parked in the Run-Test/Idle state. The update of the PARKRTI instruction MUST immediately be followed by a TMSB=0 (to enter the RTI state) in order to assure stability. When a LSPn is active (unparked), its TMSn signals follow TMSB and the LSPn controller state transitions are synchronized with the TAP Controller state transitions of the 'STA111.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 CNTRSEL: This instruction inserts the 32-bit TCK counter shift register into the active scan chain. This allows the user to program the number of n TCK cycles to send to the parked local ports once the CNTRON instruction is issued (e.g., for BIST operations). Note that to ensure completion of countdown, the 'STA111 should receive at least n TCKB pulses. CNTRON: This instruction enables the TCK counter.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com REGISTER DESCRIPTIONS INSTRUCTION REGISTER The instruction shift register is an 8-bit register that is in series with the scan chain whenever the TAP Controller of the SCANSTA111 is in the Shift-IR state. Upon exiting the Capture-IR state, the value XXXXXX01 is captured into the instruction register, where XXXXXX represents the value on the S(0-6) inputs.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 MODE REGISTER0 Mode Register0 is an 8-bit data register used primarily to configure the Local Scan Port Network. Mode Register0 is initialized to 00000001 binary upon entering the Test-Logic-Reset state. Bits 0, 1, 2, and 4 are used for scan chain configuration as described in Table 6. When the UNPARK instruction is executed, the scan chain configuration is as shown in Table 6 below.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com Bit 3 is normally set to logic 0 so that TCKn is free-running when the local scan ports are parked in the ParkedRTI, Parked-Pause-DR or Parked-Pause-IR state. When the local ports are parked, bit 3 can be programmed with logic 1, forcing all of the LSP TCKn's to stop. This feature can be used in power sensitive applications to reduce the power consumed by the test circuitry in parts of the system that are not under test.
PAGE 19
SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 This signature compactor is used to compress serial data shifted in from the local scan chain, into a 16-bit signature. This signature can then be shifted out for comparison with an expected value. This allows users to test long scan chains in parallel, via Broadcast or Multi-Cast addressing modes, and check only the 16-bit signatures from each module. The LFSR is initialized with a value of 0000 Hex upon reset.
PAGE 20
SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com BIST SUPPORT The sequence of instructions to run BIST testing on a parked SCANSTA111 port is as follows: 1. Pre-load the Boundary register of the device under test if needed. 2. Issue the CNTRSEL instruction and initialize (load) the TCK counter to 00000000 Hex. Note that the TCK counter is initialized to 00000000 Hex upon Test-Logic-Reset, so this step may not be necessary. 3.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 Figure 11. Local Scan Port Synchronization on Second Pass Figure 12. Synchronization of the Three Local Scan Ports This moves the local chain TAP Controllers to the synchronization state (Run-Test/Idle), where they stay until synchronization occurs. If the next state of the 'STA111 TAP Controller is Run-Test/Idle, TMSn is connected to TMSB and the local TAP Controllers are synchronized to the 'STA111 TAP Controller as shown in Figure 12.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com PARAMETERIZED DESIGN (HDL) In order to support a large number of applications, the 'STA111 HDL is parameterized as described: • Number of Local Scan Ports (LSPs): The 'STA111 HDL is able to simulate/synthesize a device that contains from 1 to 8 LSPs. LSP0 through LSP4 are controlled via Mode Register0 and LSP5 through LSP7 are controlled via Mode Register1.
PAGE 23
SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 SVF DRIVEN, SELF-CHECKING TEST BENCH The 'STA111 consists of 3 types of pins, dot1 backplane pins, dot1 LSP pins and support pins. The command interpreter of the test bench is able to translate a limited set of SVF commands to the dot1 backplane pins. The SVF shift commands contain both the stimulus (TDIB) and expected response (TDOB). The interpreter is able to parse the following commands: ENDDR, ENDIR, RUNTEST, SDR, SIR, STATE, TRST.
PAGE 24
SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com LSP SHARED: In the shared mode of operation, the dot1 LSP pins TDIn, TDOn and TMSn pins become GPIO pins. TMSn and TDOn are outputs, TDIn is an input in the GPIO mode. The sequence of operations to use shared GPIOs on an LSP are as follows (example uses LSP0): 1. IR-Scan the 'STA111 address into the instruction register (address a 'STA111). 2.
PAGE 25
SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 4. The TAPs are sequenced to Shift-IR and the LSB of the interrogation address is presented on the TDIB's. Concurrently, the LSBs of the ones-complement slot addresses are presented on the respective TDOB's. 5. The weak 1 being driven on U1 and U2 is overdriven by the 0 from U3. U1 and U2 enter the Wait-For-NextInterrogation state. 6. The shift operation continues and U3 finishes shifting its ones-complement address (111110) out on TDOB.
PAGE 26
SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) −0.3V to +4.0V Supply Voltage (VCC) VI = −0.5V DC Input Diode Current (IIK) −20 mA −0.5V to +3.9V DC Input Voltage (VI) VO = −0.5V DC Output Diode Current (IOK) −20 mA −0.3V to +3.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 DC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol Parameter Conditions Min Max Units VOL Maximum Low Output Voltage (TRISTB, TRIST(0-2), YB) IOUT = +100 μA 0.2 V VOL Maximum Low Output Voltage (TRISTB, TRIST(0-2), LSP_ACTIVE(0-2)) IOUT = +12 mA All Outputs Loaded 0.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply voltage and temperature ranges unless otherwise specified. Symbol Parameter Conditions Typ Max tPZL19, tPZH19 Enable Time OE to TDO(0-2) 8.5 12.0 tPLZ19, tPHZ19 Disable Time OE to TDO(0-2) 7.5 12.0 tPHL20, tPLH20 Propagation Delay OE to TRIST(0-2) 8.0 13.0 tPZL21, tPZH21 Enable Time OE to TCK(0-2) 7.5 11.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 AC LOADING AND WAVEFORMS VCC TEST SIGNAL VI 500: (tPZL, tPLZ) OPEN (tPLH, tPHL) DUT GND CL (tPZH, tPHZ) 500: Figure 14. AC Test Circuit (CL includes probe and jig capacitance) VI CL 6.0V 50pF AC Waveforms Figure 15.
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SCANSTA111 SNLS060K – AUGUST 2001 – REVISED APRIL 2013 www.ti.com Figure 16. Reset Waveforms Figure 17.
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SCANSTA111 www.ti.com SNLS060K – AUGUST 2001 – REVISED APRIL 2013 Timing Waveforms (Input Characteristics; f = 1MHz, tr = tf = 2.5ns) DATA IN VIN(H) Vmi GND OUTPUT CONTROL tpxx tpxx tPHZ VOH DATA OUT Vmo Figure 18. Waveform for Inverting and Noninverting Functions tW VIN(H) Vmi VIN(H) GND tPZH DATA OUT CONTROL IN Vmi Vmo VY Figure 19.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SCANSTA111MTX/NOPB TSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGG 48 1000 330.0 24.4 8.6 13.2 1.6 12.0 24.0 Q1 NFBGA NZA 49 2000 330.0 16.4 7.3 7.3 2.1 12.0 16.0 Q1 SCANSTA111SMX/NOPB NFBGA NZA 49 2000 330.0 16.4 7.3 7.3 2.1 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SCANSTA111MTX/NOPB TSSOP DGG 48 1000 367.0 367.0 45.0 SCANSTA111SMX NFBGA NZA 49 2000 367.0 367.0 38.0 SCANSTA111SMX/NOPB NFBGA NZA 49 2000 367.0 367.0 38.
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MECHANICAL DATA NZA0049A SLC49A (Rev B) www.ti.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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