Low Phase Noise Clock Evaluation Board User's Guide

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8 Schematics and Layout
Schematics and Layout
Figure 9. CDCE421EVM Block Switch Off
Figure 10 through Figure 14 show the printed circuit board (PCB) schematics.
Note: Board layouts are not to scale. These figures are intended to show how the board is laid
out; they are not intended to be used for manufacturing CDCE421EVM PCBs.
14 10.9MHz–1175MHz Low Phase Noise Clock Evaluation Board SCAU020 – March 2007
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