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 

  

SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Complete Pulse-Width Modulation (PWM)

Power-Control Circuitry

D Uncommitted Outputs for Single-Ended or

Push-Pull Applications

D Low Standby Current...8 mA Typ

D Interchangeable With Industry Standard

SG2524 and SG3524

description/ordering information

The SG2524 and SG3524 incorporate all the

functions required in the construction of a

regulating power supply, inverter, or switching

regulator on a single chip. They also can be used

as the control element for high-power-output

applications. The SG2524 and SG3524 were

designed for switching regulators of either polarity, transformer-coupled dc-to-dc converters, transformerless

voltage doublers, and polarity-converter applications employing fixed-frequency, pulse-width modulation

(PWM) techniques. The complementary output allows either single-ended or push-pull application. Each device

includes an on-chip regulator, error amplifier, programmable oscillator, pulse-steering flip-flop, two uncommitted

pass transistors, a high-gain comparator, and current-limiting and shutdown circuitry.

ORDERING INFORMATION

INPUT

REGULATION

PACKAGE

†

ORDERABLE TOP-SIDE

REGULATION

MAX (mV)

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP (N) Tube of 25 SG3524N SG3524N

0°Cto70°C

SOIC (D)

Tube of 40 SG3524D

SG3524

0°C to 70°C 30 SOIC (D)

Reel of 2500 SG3524DR

SG3524

SOP (NS) Reel of 2000 SG3524NSR SG3524

PDIP (N) Tube of 25 SG2524N SG2524N

–25°C to 85°C 20

SOIC (D)

Tube of 40 SG2524D

SG2524

SOIC (D)

Reel of 2500 SG2524DR

SG2524

†

Package drawings, standard packing quantities, thermal data, symboliztion, and PCB design guidelines are

available at www.ti.com/sc/package.

        

         

       

   

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

IN–

IN+

OSC OUT

CURR LIM+

CURR LIM–

GND

REF OUT

EMIT 2

COL 2

COL 1

EMIT 1

SHUTDOWN

COMP

SG2524 ...D OR N PACKAGE

SG3524 . . . D, N, OR NS PACKAGE

(TOP VIEW)

Summary of content (23 pages)

PAGE 1
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 D Complete Pulse-Width Modulation (PWM) D D D SG2524 . . . D OR N PACKAGE SG3524 . . . D, N, OR NS PACKAGE (TOP VIEW) Power-Control Circuitry Uncommitted Outputs for Single-Ended or Push-Pull Applications Low Standby Current . . .
PAGE 2
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 functional block diagram VCC 15 16 Reference Regulator REF OUT Vref 12 Vref Vref RT Oscillator CURR LIM– SHUTDOWN Comparator 9 4 5 EMIT 2 OSC OUT – CURR LIM+ 2 + COMP 1 EMIT 1 COL 2 Vref Vref IN+ 14 3 6 CT 7 IN– 11 13 T COL 1 Error Amplifier Vref + – 10 1 kΩ 10 kΩ GND 8 NOTE A: Resistor values shown are nominal.
PAGE 3
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 recommended operating conditions VCC MIN MAX Supply voltage 8 40 V Reference output current 0 50 mA –0.03 –2 mA Current through CT terminal RT CT Timing resistor 1.8 100 kΩ 0.001 0.
PAGE 4
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 error amplifier section TEST CONDITIONS† PARAMETER VIO IIB Input offset voltage SG2524 MIN TYP‡ VIC = 2.5 V VIC = 2.5 V Input bias current Open-loop voltage amplification VICR Common-mode input voltage range CMMR Common-mode rejection ratio B1 Unity-gain bandwidth MAX 0.5 5 2 10 72 80 1.8 to 3.4 TA = 25°C SG3524 MIN TYP‡ 60 MAX UNIT 2 10 mV 2 10 µA 80 dB 1.8 to 3.
PAGE 5
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 PARAMETER MEASUREMENT INFORMATION VREF 2 kΩ VCC = 8 V to 40 V 10 kΩ 15 VCC SG2524 or SG3524 2 kΩ 10 2 10 kΩ 1 9 4 1 kΩ 5 SHUTDOWN 3 OSC OUT IN+ 16 REF OUT IN– VREF 13 COL 2 CURR LIM+ CURR LIM– Outputs 12 COL 1 14 11 EMIT 1 CT RT 2 kΩ 1W 0.1 µF EMIT 2 6 2 kΩ 1W COMP 2 kΩ 7 (Open) CT RT GND 8 Figure 1.
PAGE 6
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 OPEN-LOOP VOLTAGE AMPLIFICATION OF ERROR AMPLIFIER vs FREQUENCY 90 OSCILLATOR FREQUENCY vs TIMING RESISTANCE 1M RL = ∞ VCC = 20 V TA = 25°C 80 ÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ 70 60 RL = 1 MΩ 50 RL = 300 kΩ 40 RL = 100 kΩ 30 CT = 0 CT = 0.001 µF CT = 0.003 µF CT = 0.
PAGE 7
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 PRINCIPLES OF OPERATION† The SG2524 is a fixed-frequency pulse-width-modulation (PWM) voltage-regulator control circuit. The regulator operates at a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor, CT. RT establishes a constant charging current for CT.
PAGE 8
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† synchronous operation (continued) If two or more SG2524 regulators are operated synchronously, all oscillator output terminals must be tied together. The oscillator programmed for the minimum clock period is the master from which all the other SG2524s operate.
PAGE 9
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† shutdown circuitry COMP also can be employed to introduce external control of the SG2524. Any circuit that can sink 200 µA can pull the compensation terminal to ground and, thus, disable the SG2524.
PAGE 10
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† output circuitry The SG2524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Each transistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 mA for fast response.
PAGE 11
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† VO VI VI > VO VO VI VI < VO –VO VI | +VI | < | – VO | Figure 10. Single-Ended Inductor Circuit VI ÏÏ VO VO VI Flyback Push-Pull Figure 11. Transformer-Coupled Outputs † Throughout these discussions, references to the SG2524 apply also to the SG3524.
PAGE 12
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† VCC = 15 V 15 15 kΩ 5 kΩ 0.1 µF 1 5 kΩ 5 kΩ 2 16 2 kΩ 6 SG2524 3 EMIT 1 COL 1 IN+ 12 20 µF COL 2 13 RT EMIT 2 14 CURR LIM+ . CURR LIM– OSC OUT COMP –5 V 20 mA 11 REF OUT 7 C T 10 SHUTDOWN 0.01 µF 1N916 VCC IN– 1N916 + 4 5 1N916 9 + 50 µF GND 8 Figure 12.
PAGE 13
SLVS077D – APRIL 1977 – REVISED FEBRUARY 2003 APPLICATION INFORMATION† VCC = 28 V 5 kΩ 5 kΩ IN+ 16 REF OUT 6 7 0.02 µF 11 EMIT 1 SG2524 12 COL 1 IN– 2 3 kΩ 5V 1A VCC 1 5 kΩ 0.9 mH 15 5 kΩ 0.1 µF TIP115 COL 2 RT EMIT 2 CT CURR LIM+ + 13 500 µF 1N3880 3 kΩ 14 4 10 5 SHUT CURR LIM– DOWN 3 9 OSC OUT COMP GND 0.001 µF 8 50 kΩ 0.1 Ω Input Return Figure 14.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SG2524DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SG2524DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SG3524DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SG3524NSR SO NS 16 2000 330.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SG2524DR SOIC D 16 2500 333.2 345.9 28.6 SG2524DRG4 SOIC D 16 2500 333.2 345.9 28.6 SG3524DR SOIC D 16 2500 333.2 345.9 28.6 SG3524NSR SO NS 16 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.