Datasheet

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FEATURES

DESCRIPTION

SLK2721

SLLS532B – JUNE 2002 – REVISED MARCH 2007

OC-48+FEC/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

WITH ENHANCED JITTER TOLERANCE

• Hot Plug Protection

• Fully Integrated SONET/SDH Transceiver to • Low Jitter PECL-Compatible Differential Serial

Support Clock/Data Recovery and Interface With Programmable De-Emphasis for

Multiplexer/Demultiplexer Functions the Serial Output

• Enhanced Jitter Tolerance Over SLK2701 • On-Chip Termination for LVDS and

PECL-Compatible Interface

• Supports 2.7 Gbps OC-48 FEC Rate, OC-48,

OC-24, OC-12, Gigabit Ethernet, and OC-3 • Receiver Differential Input Thresholds 150 mV

Data Rate With Autorate Detection Minimum

• Supports Transmit Only, Receiver Only, • Supports SONET Loop Timing

Transceiver and Repeater Functions in a

• Low Power <900 mW at OC-48 Data Rate

Single Chip Through Configuration Pins

• ESD Protection >2 kV

• Supports SONET/SDH Frame Detection

• 622-MHz Reference Clock

• On-Chip PRBS Generation and Verification

• Maintains Clock Output in Absence of Data

• Supports 4-Bit LVDS (OIF99.102) Electrical

• Local and Remote Loopback

Interface

• Parity Checking and Generation for the LVDS

• Single 2.5-V Power Supply

Interface

• Interfaces to Back Plane, Copper Cables, or

• 100-Pin PZP Package With PowerPAD™

Optical Modules

Design

The SLK2721 device is a single chip, multirate transceiver that derives high-speed timing signals for SONET/

SDH-based equipment. The device performs clock and data recovery, serial-to-parallel/parallel-to-serial

conversion, and a frame detection function conforming to the SONET/SDH standards.

The device can be configured to operate under OC-48, OC-24, OC-12, or OC-3 data rate through the rate

selection pins or the autorate detection function. An external reference clock operating at 622.08 MHz is

required for the recovery loop, and it also provides a stable clock source in the absence of serial data

transitions.

The SLK2721 device accepts 4-bit LVDS parallel data/clock and generates a NRZ SONET/SDH-compliant signal

at the OC-3, OC-12, OC-24, or OC-48 data rate. It also recovers the data and clock from the serial SONET

stream and demultiplexes it into 4-bit LVDS parallel data for full duplex operation. TXDATA0 and RXDATA0 are

the first bits that are transmitted and received in time, respectively. The serial interface is a low jitter,

PECL-compatible differential interface.

The SLK2721 device supports an FEC data rate up to 2.7 Gbps when configured to operate at the OC-48 data

rate and provided with an external reference clock that is properly scaled.

AVAILABLE OPTIONS

PACKAGE

(1)

PowerPAD QUAD (PZP)

–40 ° C to 85 ° C SLK2721IPZP

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI Web site at www.ti.com .

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 OC-48+FEC/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER WITH ENHANCED JITTER TOLERANCE FEATURES • • • • • • • • • Fully Integrated SONET/SDH Transceiver to Support Clock/Data Recovery and Multiplexer/Demultiplexer Functions Enhanced Jitter Tolerance Over SLK2701 Supports 2.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SLK2721 device provides a comprehensive suite of built-in tests for self-test purposes including local and remote loopback and pseudorandom bit stream (PRBS) (27-1) generation and verification.
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SLK2721 www.ti.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 TERMINAL FUNCTIONS TERMINAL NAME NO. TYPE DESCRIPTION CLOCK PINS REFCLKP REFCLKN 94 95 LVDS/PECL compatible input Differential reference input clock. There is an on-chip 100-Ω termination resistor differentially placed between REFCLKP and REFCLKN. The dc bias is also provided on-chip for the ac-coupled case. RXCLKP RXCLKN 67 68 LVDS output Receive data clock. The data on RXDATA(0:3) is on the falling edges of RXCLKP.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. TYPE DESCRIPTION PRBSEN 41 TTL input (with pulldown) PRBS testing enable. When this pin is asserted high, the device is put into the PRBS testing mode. PRBSPASS 42 TTL output PRBS test result. This pin reports the status of the PRBS test results (high = pass). When PRBSEN is disabled, the PRBSPASS pin is set low.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 DETAILED DESCRIPTION The SLK2721 device is designed to support the OC-48/24/12/3 data rates. It also supports a higher data rate that may be required for FEC support, up to 2.7 Gbps. The operating data speed can be configured through the RSEL0 and RSEL1 pins as indicated in Table 1 for normal SONET rates. For FEC support, the clock and data rates need to be scaled up as required.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 High-Speed Electrical Interface The high-speed serial I/O uses a PECL-compatible interface. The line could be directly coupled or ac-coupled. Refer to Figure 10 and Figure 11 for configuration details. As shown in the figures, an on-chip 100-. termination resistor is placed differentially at the receive end. The PECL output also provides de-emphasis for compensating ac loss when driving a cable or PCB backplane over long distance.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 Clock and Data Recovery The CDR unit of the SLK2721 device recovers the clock and data from the incoming data streams. In the event of receive data loss, the PLL automatically locks to the local REFCLK to maintain frequency stability. If the frequency of the data differs by more that 100 ppm with respect to the REFCLK frequency, the LOL pin is asserted as a warning. Actual loss of lock occurs if the data frequency differs by more than 170 ppm.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 Loss-of-Lock Indicator The SLK2721 device has a lock detection circuit to monitor the integrity of the data input. When the clock recovery loop is locked to the input serial data stream, the LOL signal goes high. If the recovered clock frequency deviates from the reference clock frequency by more than 100 ppm, LOL goes low. If the data stream clock rate deviates by more than 170 ppm, loss of lock occurs.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 Testability The SLK2721 device has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The ENABLE pin allows for all circuitry to be disabled so that an IDDQ test can be performed. The PRBS function allows for a built-in self-test (BIST).
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 Remote Loopback The RLOOP signal pin controls the remote loopback. When RLOOP is high, the serial receive data is selected and presented on the serial transmit data output pins. The serial received data is also demultiplexed and presented on the parallel receive data pins. The remote loop can be enabled only when the device is under transceiver mode.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VDD VALUE UNIT –0.3 to 3 V –0.3 to 4 V –0.3 to 3 V –0.3 to VDD + 0.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TTL VIH High-level input voltage 2 VIL Low-level input voltage IIH Input high current VDD = MAX, VIN = 2 V IIL Input low current VDD = MAX, VIN = 0.4 V –40 VOH High-level output voltage IOH = -1 mA 2.10 VOL Low-level output voltage IOH = 1 mA CI Input capacitance 3.6 V 0.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 TIMING REQUIREMENTS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 20 ppm REFERENCE CLOCK (REFCLK) Frequency tolerance (1) –20 Duty cycle 40% Jitter 60% 3 Frequency range abosolute value (1) 50% 12 kHz to 20 MHz 622.08 ps rms MHz The ±20-ppm tolerance is required to meet SONET/SDH requirements. For non-SONET/SDH-compliant systems, looser tolerances may apply.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS Figure 5. Test Load and Voltage Definitions for LVDS Outputs Figure 6. LVDS Output Waveform Figure 7. LVDS Input Waveform Figure 8.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 TYPICAL CHARACTERISTICS (continued) Figure 9. High-Speed I/O Directly-Coupled Mode Figure 10.
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SLK2721 www.ti.com SLLS532B – JUNE 2002 – REVISED MARCH 2007 APPLICATION INFORMATION DESIGNING WITH THE PowerPAD PACKAGE The SLK2721 device is housed in high-performance, thermally enhanced, 100-pin PZP PowerPAD packages. Use of a PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.