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SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Data Manual

JANUARY 2008

SPRS462B

Summary of content (254 pages)

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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Contents 1 Features.............................................................................................................................. 7 1.1 1.2 1.3 2 Device Overview................................................................................................................. 11 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 3 3.5 3.6 3.7 3.8 Device Configuration at Device Reset .......................
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 6.2 6.3 7 C64x+ Peripheral Information and Electrical Specifications ................................................... 105 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 4 Recommended Operating Conditions ..................................................................................
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 PLL2 Controller Memory Map ................................................................................ PLL2 Controller Register Descriptions ...................................................................... 7.8.3.1 PLL Controller Divider 1 Register ................................................................. 7.8.3.2 PLL Controller Command Register ..............................................
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.17 7.18 7.19 7.20 7.21 7.22 Enhanced Turbo Decoder Coprocessor (TCP2) ...................................................................... 7.17.1 TCP2 Device-Specific Information ........................................................................... 7.17.2 TCP2 Peripheral Register Description(s) ...................................................................
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 1 • • • • • • • • • (1) Features Controlled Baseline – One Assembly Site – Test Site – One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) High-Performance Fixed-Point DSP (C6455) – 1.39 ns, 1.17 ns, 1 ns, and 0.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 • • • • • System PLL and PLL Controller Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller Advanced Event Triggering (AET) Compatible Trace-Enabled Device IEEE-1149.1 (JTAG™) 1.1 • • • Boundary-Scan-Compatible 697-Pin Ball Grid Array (BGA) Package (ZTZ or GTZ Suffix), 0.8 mm Ball Pitch 0.09 µm/7-Level Cu Metal Process (CMOS) 3.3/1.8/1.5/1.25/1.2 V I/Os, 1.25/1.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16 bit x 16 bit multiply-accumulates (MACs) every clock cycle.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 1.3 Functional Block Diagram Figure 1-2 shows the functional block diagram of the C6455 device.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 2 Device Overview 2.1 Device Characteristics Table 2-1, provides an overview of the C6455 DSP. The tables show significant features of the C6455 device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type with pin count. Table 2-1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-1. Characteristics of the C6455 Processor (continued) HARDWARE FEATURES Process Technology µm Product Status (2) Product Preview (PP), Advance Information (AI), or Production Data (PD) Device Part Numbers (For more details on the C64x+™ DSP part numbering, see Figure 2-13) (2) 2.2 C6455 0.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 ÁÁ ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á www.ti.com src1 Odd register file A (A1, A3, A5...A31) src2 .L1 odd dst Even register file A (A0, A2, A4...A30) (D) even dst long src ST1b ST1a 32 MSB 32 LSB long src Data path A .S1 8 8 even dst odd dst src1 (D) src2 LD1b LD1a 32 LSB DA2 32 32 src2 32 MSB DA1 LD2a LD2b Á Á Á Á Á Á .
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 2.3 Memory Map Summary Table 2-2 shows the memory map address ranges of the C6455 device. The external memory configuration register address ranges in the C6455 device begin at the hex address location 0x7000 0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller. Table 2-2.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-2.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 2.4 Boot Sequence The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections and the DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, max reset, and system reset. For more details on the initiators of these resets, see Section 7.6, Reset Controller.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 • • • • 18 software such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host. The host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back-End Application Interrupt Enable Set Register (PCIBINTSET) and the Status Set Register (PCISTATSET).
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SRIO boot is a software boot mode. 2.4.2 2nd-Level Bootloaders Any of the boot modes can be used to download a 2nd-level bootloader. A 2nd-level bootloader allows for any level of customization to current boot methods as well as definition of a completely customized boot.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 2.5 Pin Assignments 2.5.1 Pin Map Figure 2-2 through Figure 2-5 show the C6455 pin assignments in four quadrants (A, B, C, and D).
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 2.6 Signal Groups Description CLKIN1 SYSCLK4/GP[1] (A) PLLV1 Clock/PLL1 and PLL Controller Reset and Interrupts RESETSTAT RESET NMI POR CLKIN2 PLLV2 Clock/PLL2 RSV02 RSV03 RSV04 RSV05 RSV07 RSV09 TMS TDO TDI TCK TRST Reserved EMU0 EMU1 • • • EMU14 EMU15 EMU16 EMU17 EMU18 IEEE Standard 1149.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 2.7 Terminal Functions The terminal functions table (Table 2-3) identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and a functional pin description.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) DESCRIPTION RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS RESET AG14 I Device reset NMI AH4 I RESETSTAT AE14 O Reset Status pin. The RESETSTAT pin indicates when the device is in reset POR AF14 I Power on reset.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) DESCRIPTION EMIFA (64 BIT) - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ABA1/EMIFA_EN V25 O/Z IPD EMIFA bank address control (ABA[1:0]) • Active-low bank selects for the 64 bit EMIFA. When interfacing to 16 bit Asynchronous devices, ABA1 carries bit 1 of the byte address.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME AED21 NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) DESCRIPTION ETHERNET MAC (EMAC) [RGMII] If the Ethernet MAC (EMAC) and MDIO are enabled (AEA12 driven low [UTOPIA_EN = 0]), there are two additional configuration pins — the MAC_SEL[1:0] (AEA[10:9] pins) that select one of the four interface modes (MII, RMII, GMII, or RGMII) for the EMAC/MDIO interface.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) DESCRIPTION F2 Reserved. This pin must be connected to ground (VSS) via a 200-Ω resistor for proper device operation. NOTE: If the RGMII mode of the EMAC is not used, the DVDD15, VREFHSTL, RSV13, and RSV14 pins can be connected to directly ground (VSS) to save power.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) DESCRIPTION SUPPLY VOLTAGE MONITOR PINS CVDDMON DVDD33MON DVDD15MON DVDD18MON N1 Die-side 1.2-V core supply (CVDD) voltage monitor pin. The monitor pins indicate the voltage on the die and, therefore, provide the best probe point for voltage monitoring purposes.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) U16 DVDDRM V15 S S Main SRIO supply: 1.25-V I/O supply voltage (-1000 and -1200 devices) 1.2-V I/O supply voltage (-850 and -720 devices). Do not use core supply. NOTE: If RapidIO is not used, these pins can be connected directly to VSS. A SRIO termination supply: 1.25-V I/O supply voltage (-1000 and -1200 devices) 1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) DESCRIPTION A29 E26 E28 G2 H23 H28 J6 J24 K1 K7 K23 L24 M7 M23 M28 N24 P6 P28 R1 R6 R23 DVDD33 T7 S 3.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) DESCRIPTION AD5 AD7 AD14 AD18 AD22 AD24 AE6 AE8 AE15 AF1 AF16 DVDD33 AF24 S 3.3-V I/O supply voltage S 1.25-V core supply voltage (-1000 and -1200 devices) 1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO. TYPE (1) IPD/IPU (2) DESCRIPTION R18 T11 T13 T15 T17 T19 U12 CVDD U14 S 1.25-V core supply voltage (-1000 and -1200 devices) 1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL NAME NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 2.8 2.8.1 Development Development Support In case the customer would like to develop their own features and software on the C6455 device, TI offers an extensive line of development tools for the C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, ZTZ), the temperature range (for example, blank is the default commercial temperature range), and the device speed range, in megahertz (for example, blank is 1000 MHz [1 GHz]).
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C6000 DSP platforms. SPRU970 TMS320C645x DSP DDR2 Memory Controller User's Guide. This document describes the DDR2 memory controller in the C645x digital-signal processors (DSPs). SPRU966 TMS320C645x DSP Enhanced DMA (EDMA3) Controller User's Guide. This document describes the Enhanced DMA (EDMA3) Controller on the C645x device. SPRU975 TMS320C645x DSP EMAC/MDIO Module User's Guide.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 signal processor (DSPs) of the C6000™ DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming of the TCP. 58 SPRUE48 TMS320C645x DSP Universal Test & Operations PHY Interface for ATM 2 (UTOPIA2) User's Guide.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3 Device Configuration On the C6455 device, certain device configurations like boot mode, pin multiplexing, and endianess, are selected at device reset. The status of the peripherals (enabled/disabled) is determined after device reset. By default, the peripherals on the C6455 device are disabled and need to be enabled by software before being used. 3.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION PIN NO. IPD/ IPU (1) FUNCTIONAL DESCRIPTION HPI peripheral bus width select (HPI_WIDTH). AEA14 R25 0 HPI operates in HPI16 mode (default). HPI bus is 16 bits wide; HD[15:0] pins are used and the remaining HD[31:16] pins are reserved pins in the Hi-Z state. 1 HPI operates in HPI32 mode.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION PIN NO. IPD/ IPU (1) FUNCTIONAL DESCRIPTION SYSCLKOUT Enable bit (SYSCLKOUT_EN). Selects which function is enabled on the SYSCLK4/GP[1] muxed pin.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-2.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.3 Peripheral Selection After Device Reset On the C6455 device, peripherals can be in one of several states. These states are listed in Table 3-4. Table 3-4. Peripheral States STATE DESCRIPTION PERIPHERALS THAT CAN BE IN THIS STATE Peripheral pin function has been completely disabled through the device configuration pins. Peripheral is held in reset and clock is turned off.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Static Powerdown Reset Enable In Progress Disabled Enabled Figure 3-1. Peripheral Transitions Between States Figure 3-2 shows the flow needed to change the state of a given peripheral on the C6455 device. Unlock the PERCFG0 register by using the PERLOCK register. Write to the PERCFG0 register within 16 SYSCLK3 clock cycles to change the state of the peripherals.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4 Device State Control Registers The C6455 device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 3-5 and described in the next sections. NOTE The device state control registers can only be accessed using the CPU or the emulator. Table 3-5.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.1 Peripheral Lock Register Description When written with correct 32 bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows one write to the PERCFG0 register within 16 SYSCLK3 cycles. NOTE The instructions that write to the PERLOCK and PERCFG0 registers must be in the same fetch packet if code is being executed from external memory.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.2 Peripheral Configuration Register 0 Description The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals. One write is allowed to this register within 16 SYSCLK3 cycles after the correct key is written to the PERLOCK register.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions (continued) 68 Bit Field 16 McBSP1CTL Value Description Mode control for McBSP1 0 Set McBSP1 to disabled mode 1 Set McBSP1 to enabled mode 15 Reserved Reserved. 14 McBSP0CTL Mode control for McBSP0 0 Set McBSP0 to disabled mode 1 Set McBSP0 to enabled mode 13 Reserved Reserved.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.3 Peripheral Configuration Register 1 Description The Peripheral Configuration Register (PERCFG1) is used to enable the EMIFA and DDR2 Memory Controller. EMIFA and the DDR2 Memory Controller do not have corresponding status bits in the Peripheral Status Registers. The EMIFA and DDR2 Memory Controller peripherals can be used within 16 SYSCLK3 cycles after EMIFACTL and DDR2CTL are set to 1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.4 Peripheral Status Registers Description The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6455 peripherals.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-9.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 31 16 Reserved R-0 15 6 5 3 2 0 Reserved UTOPIASTAT PCISTAT R-0 R-0 R-0 LEGEND: R = Read only; -n = value after reset Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018 Table 3-10. Peripheral Status Register 1 (PERSTAT1) Field Descriptions Bit Field Value Reserved Reserved.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.5 EMAC Configuration Register (EMACCFG) Description The EMAC Configuration Register (EMACCFG) is used to assert and deassert the reset of the Reduced Media Independent Interface (RMII) logic of the EMAC. For more details on how to use this register, see Section 7.14, Ethernet MAC (EMAC).
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers of emulator pins EMU[18:2]. These buffers can be powered down if the device trace feature is not needed.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.5 Device Status Register Description The device status register depicts the device configuration selected upon device reset. Once set, these bits will remain set until a device reset. For the actual register bit names and their associated bit field descriptions, see Figure 3-10 and Table 3-13.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Bit Field 15 SYSCLKOUT_EN 14 13 Description SYSCLKOUT Enable (SYSCLKOUT_EN) status bit Shows the status of which function is enabled on the SYSCLK4/GP[1] muxed pin.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Bit Field 3:0 BOOTMODE[3:0] 3.6 Value Description Boot mode configuration bits Shows the status of what device boot mode configuration is operational. BOOTMODE[3:0] [Note: if selected for boot, the corresponding peripheral is automatically enabled after device reset.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 3.7 Pullup/Pulldown Resistors Proper board design should ensure that input pins to the C6455 device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The C6455 device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 4 System Interconnect On the C6455 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics. The switch fabrics allow for low-latency, concurrent data transfers between master peripherals and slave peripherals.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 4.2 Data Switch Fabric Connections Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR). Masters are shown on the right and slaves on the left. The data SCR connects masters to slaves via 128 bit data buses running at a SYSCLK2 frequency.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 4-1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 4.4 Bus Priorities On the C6455 device, bus priority is programmable for each master. The register bit fields and default priority levels for C6455 bus masters are shown in Table 4-2. The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priorities.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 5 C64x+ Megamodule The C64x+ Megamodule consists of several components — the C64x+ CPU, the L1 program and data memory controllers, the L2 memory controller, the internal DMA (IDMA), the interrupt controller, power-down controller, and external memory controller.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 • Region 1 size is 32K bytes with no wait states. L1D is a two-way set-associative cache while L1P is a direct-mapped cache. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PMODE) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C64x+ Megamodule.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 5.2 Memory Protection Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (64KB each).
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 5.4 Power-Down Control The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used to design systems for lower overall system power requirements.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 5.6 Megamodule Revision The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in Figure 5-5 and described in Table 5-3. The C64x+ Megamodule revision is dependant on the silicon revision being used.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 5.7 C64x+ Megamodule Register Description(s) Table 5-4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE ACRONYM 0180 0188 INTDMASK 0180 0188 - 0180 01BC - 0180 01C0 EVTASRT 0180 01C4 - 0180 FFFF - REGISTER NAME Dropped Interrupt Mask Register Reserved Event Asserting Register Reserved Table 5-5.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-9.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-9.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-10.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) (1) Supply voltage range: CVDD (2) DVDD33 -0.5 V to 1.5 V (2) -0.5 V to 4.2 V DVDDR, DVDD18, AVDLL1, AVDLL2 (2) DVDD15 -0.5 V to 2.5 V (2) -0.5 V to 2.5 V DVDD12, DVDDRM, AVDDT, AVDDA (2) PLLV1, PLLV2 Input voltage (VI) range: -0.5 V to 1.5 V (2) -0.5 V to 2.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Recommended Operating Conditions (continued) VSS Supply ground 3.3 V pins (except PCI-capable and I2C pins) VIH High-level input voltage 0.7DVDD33 (2) 102 V DVDD33 + 0.5 V V V VREFSSTL + 0.125 DVDD18 + 0.3 V 0 0.8 V -0.5 0.3DVDD33 V 0 0.3DVDD33 V RGMII pins -0.3 VREFHSTL - 0.1 V DDR2 memory controller pins (DC) -0.3 VREFSSTL - 0.125 V -3.5 7.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) PARAMETER VOH High-level output voltage TEST CONDITIONS (1) II (3) Input current [DC] PCI-capable pins (2) IOH = -0.5 mA, DVDD33 = 3.3 V 0.9DVDD33 V DVDD15 - 0.4 V 1.4 V 3.3-V pins (except PCI-capable and I2C pins) DVDD33 = MIN, IOL = MAX 0.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information Tester Pin Electronics 42 Ω Data Sheet Timing Reference Point Output Under Test 3.5 nH Transmission Line Z0 = 50 Ω (see Note) 4.0 pF Device Pin (see Note) 1.85 pF NOTE: This data sheet provides timing at the device pin.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.1.3 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must be taken into account. Timing values may be adjusted by increasing/decreasing such delays.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 7.3 Power Supplies 7.3.1 Power-Supply Sequencing TI recommends the power-supply sequence shown in Figure 7-5.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset. It is not possible to disable these peripherals after the boot process is complete. The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+ megamodule components through its Power-Down Controller (PDC).
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.4 Enhanced Direct Memory Access (EDMA3) Controller The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.4.1 EDMA3 Device-Specific Information The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-3.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-5.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-6.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-7.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-8.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-8.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-9.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller The CPU interrupts on the C6455 device are configured through the C64x+ Megamodule Interrupt Controller. The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-10.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-10. C6455 System Event Mapping (continued) EVENT NUMBER DESCRIPTION 102 - 112 Reserved Reserved. These system events are not connected and, therefore, not used. 113 (1) L1P_ED1 L1P single bit error detected during DMA read 114 - 115 Reserved Reserved. These system events are not connected and, therefore, not used.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.5.2 External Interrupts Electrical Data/Timing Table 7-11. Timing Requirements for External Interrupts (1) (see Figure 7-6) -720 -850 A-1000/-1000 -1200 NO. MIN (1) UNIT MAX 1 tw(NMIL) Width of the NMI interrupt pulse low 6P ns 2 tw(NMIH) Width of the NMI interrupt pulse high 6P ns P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.6 Reset Controller The reset controller detects the different type of resets supported on the C6455 device and manages the distribution of those resets throughout the device. The C6455 device has several types of resets: power-on reset, warm reset, max reset, system reset, and CPU reset.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 all the system clocks are invalid at this point. – The RESETSTAT pin stays asserted (low), indicating the device is in reset. 3. The POR pin may now be deasserted (driven high). When the POR pin is deasserted, the configuration pin values are latched and the PLL controllers change their system clocks to their default divide-down values.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Section 2.4, Boot Sequence). NOTE The POR pin should be held inactive (high) throughout the Warm Reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied together with the POR pin. 7.6.3 Max Reset A Max Reset is initiated by the RapidIO peripheral and has the same affect as a Warm Reset. 7.6.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.6.6 Reset Priority If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority reset request.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.6.7 Reset Controller Register The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller. This register falls in the same memory range as the PLL1 controller registers [029A 0000 - 029A 01FF] (see Table 7-18). 7.6.7.1 Reset Type Status Register Description The rest type status (RSTYPE) register latches the cause of the last reset.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.6.8 Reset Electrical Data/Timing Table 7-14. Timing Requirements for Reset (1) (2) (3) (see Figure 7-8 and Figure 7-9) -720 -850 A-1000/-1000 -1200 NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 CLKIN1 CLKIN2 POR 6 RESET(A)(B) 9 RESETSTAT 7 8 Boot and Device Configuration Pins(C) A. RESET should only be used after device has been powered up. For more details on the use of the RESET pin, see Section 7.6, Reset Controller. B. A reset signal is generated internally during a Warm Reset. This internal reset signal has the same effect as the RESET pin during a Warm Reset. C.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7 PLL1 and PLL1 Controller The primary PLL controller generates the input clock to the C64x+ megamodule (including the CPU) as well as most of the system peripherals such as the multichannel buffered serial ports (McBSPs) and the external memory interface (EMIF).
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TMS320C6455 DSP +1.8 V PLLV1 C1 EMI Filter C2 560 pF 0.1 mF CLKIN1 (B) PLL1 PLLOUT PLLREF PLL1 Controller PLLEN (PLLCTL.[0]) DIVIDER PREDIV /1, /2, /3 ENA SYSREFCLK (C64x+ MegaModule) PLLM x1, x15, x20, x25, x30, x32 DIVIDER D2(A) 1 0 PREDEN (PREDIV.[15]) SYSCLK2 /3 DIVIDER D3(A) SYSCLK3 /6 DIVIDER D4 D4EN (PLLDIV4.[15]) /2, /4, ...
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 • • SYSCLK4 is used as the internal clock for the EMIFA. It is also used to clock other logic within the DSP. SYSCLK5 clocks the emulation and trace logic of the DSP. The divider ratio bits of dividers D2 and D3 are fixed at ÷3 and ÷6, respectively. The divider ratio bits of dividers D4 and 54 are programmable through the PLL controller divider registers PLLDIV4 and PLLDIV5, respectively.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The PLL1 lock time is given in Table 7-17. Table 7-17.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3 PLL1 Controller Register Descriptions This section provides a description of the PLL1 controller registers. For details on the operation of the PLL controller module, see the TMS320C645x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRUE56). NOTE: The PLL1 controller registers can only be accessed using the CPU or the emulator.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.2 PLL Multiplier Control Register The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20. The PLLM register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits (RATIO) in the PLL controller pre-divider register (PREDIV).
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.3 PLL Pre-Divider Control Register The PLL pre-divider control register (PREDIV) is shown in Figure 7-13 and described in Table 7-21. 31 16 Reserved R-0 15 14 5 4 0 PREDEN Reserved RATIO R/W-1 R-0 R/W-2h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-13. PLL Pre-Divider Control Register (PREDIV) [Hex Address: 029A 0114] Table 7-21.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.4 PLL Controller Divider 4 Register The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22. Besides being used as the EMIFA internal clock, SYSCLK4 is also used in other parts of the system. Disabling this clock will cause unpredictable system behavior. Therefore, the PLLDIV4 register should never be used to disable SYSCLK4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.5 PLL Controller Divider 5 Register The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15 and described in Table 7-23. 31 16 Reserved R-0 15 14 5 4 0 D5EN Reserved RATIO R/W-1 R-0 R/W-3 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-15. PLL Controller Divider 5 Register (PLLDIV5) [Hex Address: 029A 0164] Table 7-23.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.6 PLL Controller Command Register The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-16 and described in Table 7-24. 31 16 Reserved R-0 15 2 1 0 Reserved Rsvd GOSET R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-16.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.7 PLL Controller Status Register The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-17 and described in Table 7-25. 31 16 Reserved R-0 15 1 0 Reserved GOSTAT R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-17. PLL Controller Status Register (PLLSTAT) [Hex Address: 029A 013C] Table 7-25.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.8 PLL Controller Clock Align Control Register The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18 and described in Table 7-26. 31 16 Reserved R-0 15 5 4 3 2 0 Reserved ALN5 ALN4 Reserved R-0 R-1 R-1 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-18.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.9 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIVn registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE). During the GO operation, the PLL controller will only change the divide ratio of the SYSCLKs with the bit set in DCHANGE. Note that changed clocks will be automatically aligned to other clocks.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.3.10 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLKn). SYSTAT is shown in Figure 7-20 and described in Table 7-28. 31 16 Reserved R-0 15 8 Reserved R-0 7 5 4 3 2 1 0 Reserved SYS5ON SYS4ON SYS3ON SYS2ON Reserved R-0 R-1 R-1 R-1 R-1 R-1 LEGEND: R = Read only; -n = value after reset Figure 7-20.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing Table 7-29. Timing Requirements for CLKIN1 Devices (1) (2) (3) (see Figure 7-21) -720 -850 A-1000/-1000 -1200 NO. PLL MODES x1 (Bypass), x15, x20, x25, x30, x32 MIN MAX 15 30.3 UNIT 1 tc(CLKIN1) Cycle time, CLKIN1 (4) 2 tw(CLKIN1H) Pulse duration, CLKIN1 high 0.4C ns 3 tw(CLKIN1L) Pulse duration, CLKIN1 low 0.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8 PLL2 and PLL2 Controller The secondary PLL controller generates interface clocks for the Ethernet media access controller (EMAC) and the DDR2 memory controller. As shown in Figure 7-23, the PLL2 controller features a PLL multiplier controller and one divider (D1). The PLL multiplier is fixed to a x20 multiplier rate and the divider D1 can be programmed to a ÷2 or ÷5 mode.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.1 PLL2 Controller Device-Specific Information 7.8.1.1 Internal Clocks and Maximum Operating Frequencies As shown in Figure 7-23, the output of PLL2, PLLOUT, is divided by 2 and directly fed to the DDR2 memory controller. This clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUT.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.2 PLL2 Controller Memory Map The memory map of the PLL2 controller is shown in Table 7-32. Note that only registers documented here are accessible on the C6455. Other addresses in the PLL2 controller memory map should not be modified. Table 7-32. PLL2 Controller Registers HEX ADDRESS RANGE 7.8.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.3.1 PLL Controller Divider 1 Register The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-24 and described in Table 7-33. 31 16 Reserved R-0 15 14 5 4 0 D1EN Reserved RATIO R/W-1 R-0 R/W-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-24. PLL Controller Divider 1 Register (PLLDIV1) [Hex Address: 029C 0118] Table 7-33.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.3.2 PLL Controller Command Register The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-25 and described in Table 7-34. 31 16 Reserved R-0 15 2 1 0 Reserved Rsvd GOSET R-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-25.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.3.3 PLL Controller Status Register The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-26 and described in Table 7-35. 31 16 Reserved R-0 15 1 0 Reserved GOSTAT R-0 R-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-26. PLL Controller Status Register (PLLSTAT) [Hex Address: 029C 013C] Table 7-35.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.3.5 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the DCHANGE status register. During the GO operation, the PLL controller will only change the divide ratio SYSCLK1 if SYS1 in DCHANGE is 1. The PLLDIV divider ratio change status register is shown in Figure 7-28 and described in Table 7-37.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.3.6 SYSCLK Status Register The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT is shown in Figure 7-29 and described in Table 7-38. 31 16 Reserved R-0 15 1 0 Reserved SYS1ON R-0 R-1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-29. SYSCLK Status Register [Hex Address: 029C 0150] Table 7-38.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing Table 7-39. Timing Requirements for CLKIN2 (1) (2) (3) (see Figure 7-30) -720 -850 A-1000/-1000 -1200 NO. (1) (2) (3) UNIT MIN MAX 1 tc(CLKIN2) Cycle time, CLKIN2 37.5 80 2 tw(CLKIN2H) Pulse duration, CLKIN2 high 0.4C 3 tw(CLKIN2L) Pulse duration, CLKIN2 low 0.4C 4 tt(CLKIN2) Transition time, CLKIN2 1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.9 DDR2 Memory Controller The 32 bit, 533-MHz (data rate) DDR2 Memory Controller bus of the C6455 is used to interface to JESD79D-2A standard-compliant DDR2 SDRAM devices. The DDR2 external bus only interfaces to DDR2 SDRAM devices (up to 512 MB); it does not share the bus with any other types of peripherals.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.9.2 DDR2 Memory Controller Peripheral Register Description(s) Table 7-40. DDR2 Memory Controller Registers 7.9.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10 External Memory Interface A (EMIFA) The EMIFA can interface to a variety of external devices or ASICs, including: • Pipelined and flow-through Synchronous-Burst SRAM (SBSRAM) • ZBT (Zero Bus Turnaround) SRAM and Late Write SRAM • Synchronous FIFOs • Asynchronous memory, including SRAM, ROM, and Flash 7.10.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10.2 EMIFA Peripheral Register Description(s) Table 7-41.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10.3 EMIFA Electrical Data/Timing Table 7-42. Timing Requirements for AECLKIN for EMIFA (1) (2) (see Figure 7-31) -720 -850 A-1000/-1000 -1200 NO. (1) (2) (3) (4) UNIT MIN MAX 1 tc(EKI) Cycle time, AECLKIN 6 (3) 40 2 tw(EKIH) Pulse duration, AECLKIN high 2.7 3 tw(EKIL) Pulse duration, AECLKIN low 2.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module (1) (2) (3) (see Figure 7-32) NO. (1) (2) (3) -720 -850 A-1000/-1000 -1200 PARAMETER UNIT MIN MAX E - 0.7 E + 0.7 ns Pulse duration, AECLKOUT high EH - 0.7 EH + 0.7 ns Pulse duration, AECLKOUT low EL - 0.7 EL + 0.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-45. Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module (1) (2) (3) (see Figure 7-33 and Figure 7-34) NO. -720 -850 A-1000/-1000 -1200 PARAMETER MIN 1 tosu(SELV-AOEL) Output setup time, select signals valid to AAOE low RS * E – 1.5 RS * E – 1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Strobe = 4 Hold = 1 Setup = 1 AECLKOUT 12 11 ACEx 11 12 Byte Enables ABE[7:0] 11 AEA[19:0]/ ABA[1:0] 12 Address 11 12 Write Data AED[63:0] AAOE/ASOE(A) 13 13 AAWE/ASWE(A) 11 12 AR/W DEASSERTED AARDY(B) A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous memory accesses.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10.3.2 Programmable Synchronous Interface Timing Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 7-36) -720 -850 A-1000/-1000 -1200 NO. MIN 6 tsu(EDV-EKOH) Setup time, read AEDx valid before AECLKOUT high 7 th(EKOH-EDV) Hold time, read AEDx valid after AECLKOUT high UNIT MAX 2 ns 1.5 ns Table 7-47.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10.4 HOLD/HOLDA Timing Table 7-48. Timing Requirements for the HOLD/HOLDA Cycles for EMIFA Module (1) (see Figure 7-39) -720 -850 A-1000/-1000 -1200 NO. MIN 3 (1) th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low UNIT MAX E ns E = the EMIF input clock (ECLKIN) period in ns for EMIFA. Table 7-49.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.10.5 BUSREQ Timing Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module (see Figure 7-40) NO. 1 -720 -850 A-1000/-1000 -1200 PARAMETER td(AEKOH-ABUSRV) Delay time, AECLKOUT high to ABUSREQ valid MIN MAX 1 5.5 UNIT ns AECLKOUTx 1 1 ABUSREQ Figure 7-40.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.11 I2C Peripheral The inter-integrated circuit (I2C) module provides an interface between a C64x+ DSP and other devices compliant with Philips Semiconductors Inter-IC bus (I2C bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8 bit data to/from the DSP through the I2C module. 7.11.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.11.2 I2C Peripheral Register Description(s) Table 7-51.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.11.3 I2C Electrical Data/Timing 7.11.3.1 Inter-Integrated Circuits (I2C) Timing Table 7-52. Timing Requirements for I2C Timings (1) (see Figure 7-42) -720 -850 A-1000/-1000 -1200 NO. STANDARD MODE MIN MAX UNIT FAST MODE MIN MAX 1 tc(SCL) Cycle time, SCL 10 2.5 µs 2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) 4.7 0.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 11 9 SDA 6 8 14 4 13 5 10 SCL 1 12 3 2 7 3 Stop Start Repeated Start Stop Figure 7-42. I2C Receive Timings Table 7-53. Switching Characteristics for I2C Timings (1) (see Figure 7-43) NO. -720 -850 A-1000/-1000 -1200 PARAMETER STANDARD MODE MIN MAX UNIT FAST MODE MIN MAX 16 tc(SCL) Cycle time, SCL 10 2.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 26 24 SDA 21 23 19 28 20 25 SCL 16 27 18 17 22 18 Stop Start Repeated Start Stop Figure 7-43.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.12 Host-Port Interface (HPI) Peripheral 7.12.1 HPI Device-Specific Information The C6455 device includes a user-configurable 16 bit or 32 bit Host-port interface (HPI16/HPI32). The AEA14 pin controls the HPI_WIDTH, allowing the user to configure the HPI as a 16 bit or 32 bit peripheral.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.12.3 HPI Electrical Data/Timing Table 7-55. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51) -720 -850 A-1000/-1000 -1200 NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-56. Switching Characteristics for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51) NO. -720 -850 A-1000/-1000 -1200 PARAMETER MIN Case 1. HPIC or HPIA read 1 td(HSTBL-HDV) Delay time, HSTROBE low to DSP data valid MAX 5 15 Case 2. HPID read with no auto-increment (3) 9 * M + 20 Case 3.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HCS HAS HCNTL[1:0] HR/W HHWIL 13 16 16 15 15 37 37 14 13 HSTROBE(A) 3 3 1 2 1 2 HD[15:0] 38 4 7 6 HRDY(B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HCS HAS 12 11 12 11 HCNTL[1:0] 12 11 12 11 12 11 12 11 HR/W HHWIL 10 9 10 9 37 13 37 13 14 HSTROBE(A) 1 3 2 1 3 2 HD[15:0] 7 36 6 38 HRDY(B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HCS HAS HCNTL[1:0] HR/W HHWIL 16 13 16 15 37 15 37 13 14 HSTROBE(A) 18 18 17 17 HD[15:0] 4 35 38 34 5 34 5 HRDY(B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HCS HAS 12 11 12 11 HCNTL[1:0] 12 11 11 12 11 11 12 HR/W 12 HHWIL 9 10 9 14 37 HSTROBE(A) 10 37 13 13 18 18 17 17 HD[15:0] 34 35 34 5 36 5 38 HRDY(B) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HAS (input) 16 15 HCNTL[1:0] (input) HR/W (input) 13 HSTROBE(A) (input) 37 HCS (input) 1 2 3 HD[31:0] (output) 38 7 6 4 HRDY(B) (output) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 10 HAS (input) 12 11 HCNTL[1:0] (input) HR/W (input) 9 13 HSTROBE(A) (input) 37 HCS (input) 1 2 3 HD[31:0] (output) 7 38 6 36 HRDY(B) (output) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 HAS (input) 16 15 HCNTL[1:0] (input) HR/W (input) 13 HSTROBE(A) (input) 37 HCS (input) 18 17 HD[31:0] (input) 38 34 35 5 4 HRDY(B) (output) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 10 HAS (input) 12 11 HCNTL[1:0] (input) HR/W (input) 9 13 HSTROBE(A) (input) 37 HCS (input) 17 18 HD[31:0] (input) 35 36 34 38 5 HRDY(B) (output) A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. B.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.13.1 McBSP Device-Specific Information The CLKS signal is shared by both McBSP0 and McBSP1 on this device. Also, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater. The McBSP Data Receive Register (DRR) and Data Transmit Register (DXR) can be accessed through two separate busses: a configuration bus and a data bus.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-58.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.13.2 McBSP Electrical Data/Timing 7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing Table 7-59. Timing Requirements for McBSP (1) (see Figure 7-52) -720 -850 A-1000/-1000 -1200 NO. MIN (1) (2) (3) (4) UNIT MAX 2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 6P or 10 (2) (3) ns 3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP (see Figure 7-52) (continued) NO. -720 -850 A-1000/-1000 -1200 PARAMETER MIN ns CLKX int –1.7 3 CLKX ext 1.7 9 CLKX int –3.9 4 CLKX ext 2.1 9 CLKX int –3.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 CLKS 1 2 3 3 CLKR 4 4 FSR (int) 5 6 FSR (ext) 7 DR 8 Bit(n-1) (n-2) (n-3) 2 3 3 CLKX 9 FSX (int) 11 10 FSX (ext) FSX (XDATDLY=00b) 14 13 (A) Bit(n-1) 12 DX Bit 0 A. Parameter No. 13 applies to the first data bit only when XDATDLY ≠ 0. B. The CLKS signal is shared by both McBSP0 and McBSP1 on this device. 13 (A) (n-2) (n-3) Figure 7-52. McBSP Timing(B) Table 7-61.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-62. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 (1) (2) (see Figure 7-54) -720 -850 A-1000/-1000 -1200 NO. MASTER MIN (1) (2) 4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 5 th(CKXL-DRV) Hold time, DR valid after CLKX low UNIT SLAVE MAX MIN MAX 12 2 – 18P ns 4 5 + 36P ns P = 1/CPU clock frequency in ns.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-64. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 (1) (2) (see Figure 7-55) -720 -850 A-1000/-1000 -1200 NO. UNIT MASTER MIN (1) (2) 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 5 th(CKXH-DRV) Hold time, DR valid after CLKX high SLAVE MAX MIN MAX 12 2 – 18P ns 4 5 + 36P ns P = 1/CPU clock frequency in ns.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-66. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 (1) (2) (see Figure 7-56) -720 -850 A-1000/-1000 -1200 NO. MASTER MIN (1) (2) 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 5 th(CKXH-DRV) Hold time, DR valid after CLKX high UNIT SLAVE MAX MIN MAX 12 2 – 18P ns 4 5 + 36P ns P = 1/CPU clock frequency in ns.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-68. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 (1) (2) (see Figure 7-57) -720 -850 A-1000/-1000 -1200 NO. MASTER MIN (1) (2) 4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 5 th(CKXH-DRV) Hold time, DR valid after CLKX high UNIT SLAVE MAX MIN MAX 12 2 – 18P ns 4 5 + 36P ns P = 1/CPU clock frequency in ns.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14 Ethernet MAC (EMAC) The Ethernet Media Access Controller (EMAC) module provides an efficient interface between the C6455 DSP core processor and the networked community.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.1 EMAC Device-Specific Information Interface Modes The EMAC module on the C6455 supports four interface modes: Media Independent Interface (MII), Reduced Media Independent Interface (RMII), Gigabit Media Independent Interface (GMII), and Reduced Gigabit Media Independent Interface (RGMII). The MII and GMII interface modes are defined in the IEEE 802.3-2002 standard.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-70.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate the clocks to the EMAC module in RGMII or GMII mode. When the EMAC is enabled with these modes, the input clock to the PLL2 Controller (CLKIN2) must have a 25-MHz frequency. For more information, see Section 7.8, PLL2 and PLL2 Controller.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.2 EMAC Peripheral Register Description(s) Table 7-71.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-72.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.3 EMAC Electrical Data/Timing 7.14.3.1 EMAC MII and GMII Electrical Data/Timing Table 7-75. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 7-59) -720 -850 A-1000/-1000 -1200 NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-77. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII Operation (see Figure 7-61) -720 -850 A-1000/-1000 -1200 NO. UNIT 1000 Mbps MIN MAX 1 tc(GMTCLK) Cycle time, GMTCLK 8 ns 2 tw(GMTCLKH) Pulse duration, GMTCLK high 2.8 ns 3 tw(GMTCLKL) Pulse duration, GMTCLK low 2.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-79. Switching Characteristics Over Recommended Operating Conditions for EMAC MII and GMII Transmit 10/100 Mbit/s (1) (see Figure 7-63) NO. -720 -850 A-1000/-1000 -1200 PARAMETER UNIT 100/10 Mbps 1 (1) td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid MIN MAX 5 25 ns For MII, Transmit selected signals include: MTXD[3:0] and MTXEN.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.3.2 EMAC RMII Electrical Data/Timing The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation. The RMREFCLK frequency should be 50 MHz ±50 PPM with a duty cycle between 35% and 65%, inclusive. Table 7-81. Timing Requirements for RMREFCLK - RMII Operation (see Figure 7-65) NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps (1) (see Figure 7-67) -720 -850 A-1000/-1000 -1200 NO. MIN (1) 1 tsu(MRXD-MREFCLK) Setup time, receive selected signals valid before MREFCLK (at DSP) high/low 2 th(MREFCLK-MRXD) Hold time, receive selected signals valid after MREFCLK (at DSP) high/low UNIT MAX 4.0 ns 2.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.3.3 EMAC RGMII Electrical Data/Timing An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user. Note that this reference clock is not a free-running clock. This should only be used by an external device if it does not expect a valid clock during device reset. Table 7-84.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-86. Timing Requirements for EMAC RGMII Input Receive for 10/100/1000 Mbps (1) (see Figure 7-69) -720 -850 A-1000/-1000 -1200 NO. MIN (1) UNIT MAX 5 tsu(RXD-RXCH) Setup time, receive selected signals valid before RXC (at DSP) high/low 1.0 ns 6 th(RXCH-RXD) Hold time, receive selected signals valid after RXC (at DSP) high/low 1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-88. Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit (1)(see Figure 7-70) NO. -720 -850 A-1000/-1000 -1200 PARAMETER MIN (1) 5 tsu(TXD-TXCH) Setup time, transmit selected signals valid before TXC (at DSP) high/low 1.2 6 th(TXCH-TXD) Hold time, transmit selected signals valid after TXC (at DSP) high/low 1.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.4 Management Data Input/Output (MDIO) The Management Data Input/Output (MDIO) module implements the 802.3 serial management interface to interrogate and controls up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.14.4.3 MDIO Electrical Data/Timing Table 7-90. Timing Requirements for MDIO Input (R)(G)MII (see Figure 7-71) -720 -850 A-1000/-1000 -1200 NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.15 Timers The timers can be used to: time events, count events, generate pulses, interrupt the CPU, and send synchronization events to the EDMA3 channel controller. 7.15.1 Timers Device-Specific Information The C6455 device has two general-purpose timers, Timer0 and Timer1, each of which can be configured as a general-purpose timer or a watchdog timer.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.15.3 Timers Electrical Data/Timing Table 7-94. Timing Requirements for Timer Inputs (1) (see Figure 7-73) -720 -850 A-1000/-1000 -1200 NO. MIN (1) UNIT MAX 1 tw(TINPH) Pulse duration, TINPLx high 12P ns 2 tw(TINPL) Pulse duration, TINPLx low 12P ns P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns. Table 7-95.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) 7.16.1 VCP2 Device-Specific Information The C6455 device has a high-performance embedded coprocessor [Viterbi-Decoder Coprocessor (VCP2) that significantly speeds up channel-decoding operations on-chip. The VCP2 operating at CPU clock divided-by-4 can decode over 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-96. VCP2 Registers (continued) EDMA BUS HEX ADDRESS RANGE CONFIGURATION BUS HEX ADDRESS RANGE ACRONYM 5800 1000 - BM Branch Metrics 5800 2000 - SM State Metric 5800 3000 - TBHD Traceback Hard Decision 5800 6000 - TBSD Traceback Soft Decision 5800 F000 - IO REGISTER NAME Decoded Bits 7.17 Enhanced Turbo Decoder Coprocessor (TCP2) 7.17.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.17.2 TCP2 Peripheral Register Description(s) Table 7-97.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.18 Peripheral Component Interconnect (PCI) The C6455 DSP supports connections to a PCI backplane via the integrated PCI master/slave bus interface. The PCI port interfaces to DSP internal resources via the data switched central resource. The data switched central resource is described in more detail in Section 4.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.18.2 PCI Peripheral Register Description(s) Table 7-99.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-100.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-100. PCI Back End Configuration Registers (continued) DSP ACCESS HEX ADDRESS RANGE ACRONYM 02C0 0308 PCIMCFGCMD 02C0 030C - 02C0 030F - 02C0 0310 PCIMSTCFG DSP ACCESS REGISTER NAME PCI Master Configuration/IO Access Command Register Reserved PCI Master Configuration Register Table 7-101.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-102.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-103.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.18.3 PCI Electrical Data/Timing Texas Instruments (TI) has performed the simulation and system characterization to ensure that the PCI peripheral meets all AC timing specifications as required by the PCI Local Bus Specification (version 2.3). The AC timing specifications are not reproduced here. For more information on the AC timing specifications, see section 4.2.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.19 UTOPIA 7.19.1 UTOPIA Device-Specific Information The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8 Bit Slave-only interface. The UTOPIA is more simplistic than the Ethernet MAC, in that the UTOPIA is serviced directly by the EDMA3 controller.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.19.3 UTOPIA Electrical Data/Timing Table 7-106. Timing Requirements for UXCLK (1) (see Figure 7-74) -720 -850 A-1000/-1000 -1200 NO. MIN (1) UNIT MAX 1 tc(UXCK) Cycle time, UXCLK 20 2 tw(UXCKH) Pulse duration, UXCLK high 0.4tc(UXCK) 0.6tc(UXCK) ns ns 3 tw(UXCKL) Pulse duration, UXCLK low 0.4tc(UXCK) 0.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-108. Timing Requirements for UTOPIA Slave Transmit (see Figure 7-76) -720 -850 A-1000/-1000 -1200 NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-110. Timing Requirements for UTOPIA Slave Receive (see Figure 7-77) -720 -850 A-1000/-1000 -1200 NO.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.20 Serial RapidIO (SRIO) Port The SRIO port on the C6455 device is a high-performance, low pin-count interconnect aimed for embedded markets. The use of the Rapid I/O interconnect in a baseband board design can create a homogeneous interconnect environment, providing even more connectivity and control among the components.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
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www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TI only supports designs that follow the board design guidelines outlined in the SPRAAA8 application report.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.21 General-Purpose Input/Output (GPIO) 7.21.1 GPIO Device-Specific Information On the C6455 the GPIO peripheral pins GP[15:8] and GP[3:0] are muxed with the UTOPIA, PCI, and McBSP1 peripheral pins and the SYSCLK4 signal. For more detailed information on device/peripheral configuration and the C6455 device pin muxing, see Section 3, Device Configuration. 7.21.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.21.3 GPIO Electrical Data/Timing Table 7-114. Timing Requirements for GPIO Inputs (1) (2) (see Figure 7-78) -720 -850 A-1000/-1000 -1200 NO. MIN (1) (2) UNIT MAX 1 tw(GPIH) Pulse duration, GPIx high 12P ns 2 tw(GPIL) Pulse duration, GPIx low 12P ns P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.22 Emulation Features and Capability 7.22.1 Advanced Event Triggering (AET) The C6455 device supports Advanced Event Triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.22.3 IEEE 1149.1 JTAG 7.22.3.1 JTAG Device-Specific Information 7.22.3.1.1 IEEE 1149.1 JTAG Compatibility Statement For maximum reliability, the C6455 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data sheet revision history highlights the technical changes made to the SPRS276G device-specific data sheet to make it an SPRS276H revision. Scope: Applicable updates to the C64x device family, specifically relating to the SM320C6455-EP device, have been incorporated.
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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR www.ti.com SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 8 Mechanical Data 8.1 Thermal Data Table 8-1 shows the thermal resistance characteristics for the PBGA - ZTZ/GTZ mechanical package. Table 8-1. Thermal Resistance Characteristics (S-PBGA Package) [ZTZ/GTZ] NO. N/A RΘJC Junction-to-case 1.45 2 RΘJB Junction-to-board 8.34 N/A 16.1 0.00 13.0 1.0 11.9 2.0 4 5 RΘJA Junction-to-free air 6 7 8 8.
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PACKAGE OPTION ADDENDUM www.ti.
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