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7.20 Serial RapidIO (SRIO) Port
7.20.1 Serial RapidIO Device-Specific Information
7.20.2 Serial RapidIO Peripheral Register Description(s)
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
The SRIO port on the C6455 device is a high-performance, low pin-count interconnect aimed for
embedded markets. The use of the Rapid I/O interconnect in a baseband board design can create a
homogeneous interconnect environment, providing even more connectivity and control among the
components. Rapid I/O is based on the memory and device addressing concepts of processor buses
where the transaction processing is managed completely by hardware. This enables the Rapid I/O
interconnect to lower the system cost by providing lower latency, reduced overhead of packet data
processing, and higher system bandwidth, all of which are key for wireless interfaces. The Rapid I/O
interconnect offers very low pin-count interfaces with scalable system bandwidth based on 10-Gigabit per
second (Gbps) bidirectional links.
The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each
serial link consists of a differential pair), the 8 bit/10 bit encoder/decoder, the PLL clock recovery, and the
parallel-to-serial/serial-to-parallel converters.
The RapidIO interface should be designed to operate at a data rate of 3 125 Gbps per differential pair.
This equals 12.5 raw GBaud/s for the 4x RapidIO port, or approximately 9 Gbps data throughput rate.
The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as
EMIF, HPI, and McBSP. For these other interfaces the device timing was specified in terms of data
manual specifications and I/O buffer information specification (IBIS) models.
For the C6455 SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing
two DSPs connected via a 4x SRIO link directly to the user. TI has performed the simulation and system
characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system
solution is documented in the Implementing Serial Rapid I/O PCB Layout on a TMS320C6455 Hardware
Design application report (literature number SPRAAA8 ).
TI only supports designs that follow the board design guidelines outlined in the SPRAAA8
application report.
The Serial RapidIO peripheral is a master peripheral in the C6455 DSP. It conforms to the RapidIO™
Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Revision 1.2.
If the SRIO peripheral is not used, the SRIO reference clock inputs and SRIO link pins can be left
unconnected. If the SRIO peripheral is enabled but not all links are used, the pins of the unused links can
be left unconnected and no terminations are needed. For more information, see the TMS320C6455
Design Guide and Comparisons to TMS320TC6416T (literature number SPRAA89 ).
Table 7-112. RapidIO Control Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
02D0 0000 RIO_PID Peripheral Identification Register
02D0 0004 RIO_PCR Peripheral Control Register
02D0 0008 - 02D0 001C - Reserved
02D0 0020 RIO_PER_SET_CNTL Peripheral Settings Control Register
02D0 0024 - 02D0 002C - Reserved
02D0 0030 RIO_GBL_EN Peripheral Global Enable Register
02D0 0034 RIO_GBL_EN_STAT Peripheral Global Enable Status
02D0 0038 RIO_BLK0_EN Block Enable 0
02D0 003C RIO_BLK0_EN_STAT Block Enable Status 0
02D0 0040 RIO_BLK1_EN Block Enable 1
02D0 0044 RIO_BLK1_EN_STAT Block Enable Status 1
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