Car Stereo System - Car Radio Digital Signal Processor User Manual
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
7.8.2 PLL2 Controller Memory Map ................................................................................ 153
7.8.3 PLL2 Controller Register Descriptions ...................................................................... 153
7.8.3.1 PLL Controller Divider 1 Register ................................................................. 154
7.8.3.2 PLL Controller Command Register ............................................................... 155
7.8.3.3 PLL Controller Status Register .................................................................... 156
7.8.3.4 PLL Controller Clock Align Control Register ..................................................... 156
7.8.3.5 PLLDIV Ratio Change Status Register ........................................................... 157
7.8.3.6 SYSCLK Status Register ........................................................................... 158
7.8.4 PLL2 Controller Input Clock Electrical Data/Timing ....................................................... 159
7.9 DDR2 Memory Controller ................................................................................................ 160
7.9.1 DDR2 Memory Controller Device-Specific Information ................................................... 160
7.9.2 DDR2 Memory Controller Peripheral Register Description(s) ............................................ 161
7.9.3 DDR2 Memory Controller Electrical Data/Timing .......................................................... 161
7.10 External Memory Interface A (EMIFA) ................................................................................. 162
7.10.1 EMIFA Device-Specific Information .......................................................................... 162
7.10.2 EMIFA Peripheral Register Description(s) .................................................................. 163
7.10.3 EMIFA Electrical Data/Timing ................................................................................ 164
7.10.3.1 Asynchronous Memory Timing .................................................................. 165
7.10.3.2 Programmable Synchronous Interface Timing ................................................ 168
7.10.4 HOLD/ HOLDA Timing ......................................................................................... 171
7.10.5 BUSREQ Timing ............................................................................................... 172
7.11 I2C Peripheral ............................................................................................................. 173
7.11.1 I2C Device-Specific Information .............................................................................. 173
7.11.2 I2C Peripheral Register Description(s) ...................................................................... 175
7.11.3 I2C Electrical Data/Timing .................................................................................... 176
7.11.3.1 Inter-Integrated Circuits (I2C) Timing .......................................................... 176
7.12 Host-Port Interface (HPI) Peripheral ................................................................................... 179
7.12.1 HPI Device-Specific Information ............................................................................. 179
7.12.2 HPI Peripheral Register Description(s) ...................................................................... 179
7.12.3 HPI Electrical Data/Timing .................................................................................... 180
7.13 Multichannel Buffered Serial Port (McBSP) ........................................................................... 190
7.13.1 McBSP Device-Specific Information ......................................................................... 191
7.13.1.1 McBSP Peripheral Register Description(s) ..................................................... 191
7.13.2 McBSP Electrical Data/Timing ............................................................................... 193
7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing ......................................... 193
7.14 Ethernet MAC (EMAC) ................................................................................................... 200
7.14.1 EMAC Device-Specific Information .......................................................................... 201
7.14.2 EMAC Peripheral Register Description(s) .................................................................. 204
7.14.3 EMAC Electrical Data/Timing ................................................................................. 208
7.14.3.1 EMAC MII and GMII Electrical Data/Timing .................................................. 208
7.14.3.2 EMAC RMII Electrical Data/Timing .............................................................. 211
7.14.3.3 EMAC RGMII Electrical Data/Timing ............................................................ 213
7.14.4 Management Data Input/Output (MDIO) ................................................................... 216
7.14.4.1 MDIO Device-Specific Information .............................................................. 216
7.14.4.2 MDIO Peripheral Register Description(s) ....................................................... 216
7.14.4.3 MDIO Electrical Data/Timing ..................................................................... 217
7.15 Timers ...................................................................................................................... 218
7.15.1 Timers Device-Specific Information .......................................................................... 218
7.15.2 Timers Peripheral Register Description(s) .................................................................. 218
7.15.3 Timers Electrical Data/Timing ................................................................................ 219
7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) ..................................................................... 220
7.16.1 VCP2 Device-Specific Information ........................................................................... 220
7.16.2 VCP2 Peripheral Register Description(s) ................................................................... 220
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