Car Stereo System - Car Radio Digital Signal Processor User Manual

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Shadingdenotesaperipheralmodulenotavailableforthisconfiguration.
UTOPIA
McBSP0
TIMER0
EMIFA
GPIO
TIMER1
PLL1
andPLL1
Controller
DDR2
EMIF
VCP2
AED[63:0]
64
AECLKIN, AARDY, AHOLD
AEA[22:3], ACE[3:0], ABE[7:0],
AECLKOUT, ASDCKE,
AHOLDA, ABUSREQ,
ASADS
/ASRE, AAOE/ASOE,
AAWE
/ASWE
SCL
SDA
CLKIN1,PLLV1
SYSCLK4
RIOCLK,RIOCLK,RIOTX[3:0],
RIOTX[3:0]
,RIORX[3:0],RIORX[3:0]
HRDY,HINT
HCNTL0,HCNTL1,HHWIL,
HAS
,HR/W,HCS,HDS1,HDS2
CLKR0,FSR0,DR0,CLKS0,
DX0,FSX0,CLKX0
MRXD[7:0],MRXER,MRXDV,MCOL,
MCRS,MTCLK,MRCLK
32
HD[31:0]
TCP2
CLKIN2,PLLV2
GP[15:12,2,1]
DEA[21:2],DCE[1:0],DBE[3:0],DDRCLK,DDRCLK,
DSDCKE,DDQS,DDQS
,DSDCAS,DSDRAS,
DSDWE
AEA[19:16](BOOTMODE[3:0])=0001,(HPIBoot)
AEA[15](AECLKIN_SEL)=0,(AECLKIN,default)
AEA[14](HPI_WIDTH)=1,(HPI,32-bitOperation)
AEA[13](LENDIAN)=IPU,(LittleEndianMode,default)
AEA[12](UTOPIA_EN)=0,(UTOPIA disabled,default)
AEA[11]=1(mustopposeIPD)
AEA[8](PCI_EEAI)=0,(PCII2CEEPROM Auto-Initdisabled,default)
AEA[7]=0,(donotopposeIPD)
AEA[6](PCI66)=0,(PCI33MHz[default,don’tcare])
AEA[5](MCBSP1_EN)=1,(McBSP1enabled)
AEA[4](SYSCLKOUT_EN)=1,(SYSCLK4pinfunction)
AEA[3] =1(mustopposeIPD)
McBSP1
EMAC
RapidIO
32
ED[31:0]
TINP1L
TOUT1L
TOUT0
TINP0
MTXD[7:0],MTXEN,
MDIO,MDCLK
MDIO
I2C
PCI
HPI
(32-Bit)
CLKR1,FSR1,DR1,CLKS1,
DX1,FSX1,CLKX1
DEVSTAT Register:0x0061 C161
PCI_EN=0(PCIdisabled,default)
ABA1(EMIFA_EN)=1(EMIFA enabled)
ABA0(DDR2_EN)=1(DDR2MemoryControllerenabled)
PLL2
andPLL2
Controller
AEA[10:9](MACSEL[1:0])=00,(10/100MIIMode) AEA[2:0](CFGGP[2:0])=000(default)
SM320C6455-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008
Figure 3-13. Configuration Example B (2 McBSPs + HPI32 + I2C + EMIFA + DDR2 Memory Controller +
TIMERS + RapidIO + EMAC (GMII) + MDIO
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