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SLLS534B − MAY 2002 − REVISED OCTOBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Operates With 3-V to 5.5-V V

Supply

D Operates Up To 1 Mbit/s

D Low Standby Current...1 µA Typ

D External Capacitors ...4 × 0.1 µF

D Accepts 5-V Logic Input With 3.3-V Supply

D RS-232 Bus-Pin ESD Protection Exceeds

±15 kV Using Human-Body Model (HBM)

D Applications

− Battery-Powered Systems, PDAs,

Notebooks, Laptops, Palmtop PCs, and

Hand-Held Equipment

description/ordering information

The SN65C3222 and SN75C3222 consist of two line drivers, two line receivers, and a dual charge-pump circuit

with ±15-kV ESD protection pin to pin (serial-port connection pins, including GND). The devices provide the

electrical interface between an asynchronous communication controller and the serial-port connector. The

charge pump and four small external capacitors allow operation from a single 3-V to 5.5-V supply. The devices

operate at data signaling rates up to 1 Mbit/s and a driver output slew rate of 24 V/µs to 150 V/µs.

The SN65C3222 and SN75C3222 can be placed in the power-down mode by setting PWRDOWN

low, which

draws only 1 µA from the power supply. When the devices are powered down, the receivers remain active while

the drivers are placed in the high-impedance state. Also, during power down, the onboard charge pump is

disabled, V+ is lowered to V

, and V− is raised toward GND. Receiver outputs also can be placed in the

high-impedance state by setting EN

high.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC (DW)

Tube of 25 SN75C3222DW

75C3222

SOIC (DW)

Reel of 2000 SN75C3222DWR

75C3222

−0°C to 70°C

SSOP (DB) Reel of 2000 SN75C3222DBR CA3222

−0 C to 70 C

TSSOP (PW)

Tube of 70 SN75C3222PW

CA3222

TSSOP (PW)

Reel of 2000 SN75C3222PWR

CA3222

SOIC (DW)

Tube of 25 SN65C3222DW

65C3222

SOIC (DW)

Reel of 2000 SN65C3222DWR

65C3222

−40°C to 85°C

SSOP (DB) Reel of 2000 SN65C3222DBR CB3222

−40 C to 85 C

TSSOP (PW)

Tube of 70 SN65C3222PW

CB3222

TSSOP (PW)

Reel of 2000 SN65C3222PWR

CB3222

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DB, DW, OR PW PACKAGE

(TOP VIEW)

C1+

V+

C1−

C2+

C2−

V−

DOUT2

RIN2

ROUT2

PWRDOWN

GND

DOUT1

RIN1

ROUT1

DIN1

DIN2

NC − No internal connection

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Summary of content (19 pages)

PAGE 1
SLLS534B − MAY 2002 − REVISED OCTOBER 2004 D D D D D D D DB, DW, OR PW PACKAGE (TOP VIEW) Operates With 3-V to 5.5-V VCC Supply Operates Up To 1 Mbit/s Low Standby Current . . . 1 µA Typ External Capacitors . . . 4 × 0.1 µF Accepts 5-V Logic Input With 3.
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SLLS534B − MAY 2002 − REVISED OCTOBER 2004 Function Tables EACH DRIVER INPUTS DIN OUTPUT DOUT PWRDOWN X L Z L H H H H L H = high level, L = low level, X = irrelevant, Z = high impedance EACH RECEIVER INPUTS RIN EN OUTPUT ROUT H L L H L L X H Z Open L H H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = input disconnected or connected driver off logic diagram (positive lo
PAGE 3
SLLS534B − MAY 2002 − REVISED OCTOBER 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Positive output supply voltage range, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 4
SLLS534B − MAY 2002 − REVISED OCTOBER 2004 DRIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 5) PARAMETER TEST CONDITIONS MIN TYP† VOH VOL High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 5.4 Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC −5 −5.
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SLLS534B − MAY 2002 − REVISED OCTOBER 2004 RECEIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 5) PARAMETER VOH VOL MIN TYP† VCC − 0.6 V VCC − 0.1 V TEST CONDITIONS High-level output voltage IOH = −1 mA IOL = 1.6 mA Low-level output voltage VIT+ Positive-going input threshold voltage VCC = 3.
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SLLS534B − MAY 2002 − REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION 3V Input Generator (see Note B) 1.5 V RS-232 Output 50 Ω RL 1.5 V 0V CL (see Note A) 3V PWRDOWN tTHL tTLH VOH 3V 3V Output −3 V −3 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS SR(tr) + t THL 6V or t TLH NOTES: A. CL includes probe and jig capacitance. B.
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SLLS534B − MAY 2002 − REVISED OCTOBER 2004 PARAMETER MEASUREMENT INFORMATION VCC S1 GND RL Output 3 V or 0 V CL (see Note A) EN 3V Input 1.5 V −3 V tPZH (S1 at GND) tPHZ S1 at GND) VOH Output 50% 0.3 V Generator (see Note B) 1.5 V 50 Ω tPLZ (S1 at VCC) 0.3 V Output 50% VOL tPZL (S1 at VCC) TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B.
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SLLS534B − MAY 2002 − REVISED OCTOBER 2004 APPLICATION INFORMATION 1 EN 2 20 Powerdown VCC C1+ PWRDOWN 19 + C BYPASS = 0.1 µF + C1 − 3 + V+ GND 18 − C3† − 4 5 17 C1− 16 C2+ DOUT1 RIN1 + C2 − 6 7 C4 DOUT2 RIN2 ROUT2 − 15 C2− 14 V− ROUT1 NC + 8 13 9 12 10 11 DIN1 DIN2 NC † C3 can be connected to VCC or GND. NOTES: A. Resistor values shown are nominal. B.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-Oct-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65C3222DBR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN65C3222DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN65C3222PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 12-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65C3222DBR SSOP DB 20 2000 367.0 367.0 38.0 SN65C3222DWR SOIC DW 20 2000 367.0 367.0 45.0 SN65C3222PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN75C3222DWR SOIC DW 20 2000 367.0 367.0 45.0 SN75C3222PWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.