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FEATURES DESCRIPTION

APPLICATIONS

FUNCTIONAL DIAGRAM

EYE PATTERN

1.5 Gbps

-1 PRBS

750 MHz

= 3.3 V, T

= 25°C, V

 = 200 mV, V

= 1.2 V, V

= 3.3 V, R

= 50 Ω

Vertical Scale = 500 mV/div

Horizontal Scale = 200 ps/div

SN65CML100

SLLS547 – NOVEMBER 2002

1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER

• Provides Level Translation From LVDS or

This high-speed translator/repeater is designed for

LVPECL to CML, Repeating From CML to CML

signaling rates up to 1.5 Gbps to support various

high-speed network routing applications. The driver

• Signaling Rates

(1)

up to 1.5 Gbps

output is compatible with current-mode logic (CML)

• CML Compatible Output Directly Drives

levels, and directly drives 50- Ω or 25- Ω loads

Devices With 3.3-V, 2.5-V, or 1.8-V Supplies

connected to 1.8-V, 2.5-V, or 3.3-V nominal supplies.

• Total Jitter < 70 ps

The capability for direct connection to the loads may

eliminate the need for coupling capacitors. The

• Low 100 ps (Max) Part-To-Part Skew

receiver input is compatible with LVDS (TIA/EIA-644),

• Wide Common-Mode Receiver Capability

LVPECL, and CML signaling levels. The receiver

Allows Direct Coupling of Input Signals

tolerates a wide common-mode voltage range, and

• 25 mV of Receiver Input Threshold Hysteresis

may also be directly coupled to the signal source.

Over 0-V to 4-V Common-Mode Range

The internal data path from input to output is fully

differential for low noise generation and low

• Propagation Delay Times, 800 ps Maximum

pulse-width distortion.

• 3.3-V Supply Operation

The V

pin is an internally generated voltage supply

• Available in SOIC and MSOP Packages

to allow operation with a single-ended LVPECL input.

For single-ended LVPECL input operation, the

unused differential input is connected to V

as a

• Level Translation

switching reference voltage. When used, decouple

• 622-MHz Central Office Clock Distribution

with a 0.01- µ F capacitor and limit the current

sourcing or sinking to 400 µ A. When not used, V

BB• High-Speed Network Routing

should be left open.

• Wireless Basestations

This device is characterized for operation from –40 ° C

• Low Jitter Clock Repeater

(1)

to 85 ° C.

(1) The signaling rate of a line is the number of voltage

transitions that are made per second expressed in the units

bps (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER FEATURES • • • • • • • • • • DESCRIPTION Provides Level Translation From LVDS or LVPECL to CML, Repeating From CML to CML Signaling Rates(1) up to 1.5 Gbps CML Compatible Output Directly Drives Devices With 3.3-V, 2.5-V, or 1.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 DEVICE CHARACTERISTICS PARAMETER ICC Supply current, device only VBB Switching reference voltage (1) (1) MIN NOM MAX UNIT 9 12 mA 1890 1950 2010 mV VBB parameter varies 1:1 with VCC INPUT ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER Positive-going differential input voltage threshold VIT+ mV –100 VID(HYS) Differential input voltage hysteresis,VIT+ – VIT– 25 VI = 0 V or 2.
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SN65CML100 www.ti.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 PARAMETER MEASUREMENT INFORMATION IIA A Y B Z VID VIA+VIB VIC VOD VIA VIB 2 VOY VOY+VOZ VOZ IIB 2 Figure 1. Voltage and Current Definitions Table 1. Maximum Receiver Input Voltage Threshold APPLIED VOLTAGES (1) RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE VID VIC OUTPUT (1) VIA VIB 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V L 4.0 V 3.9 V 100 mV 3.95 V H 3.9 V 4. 0 V –100 mV 3.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 RT1 A Y 1 pF VID VIA B VOY Z VIB VTT RT2 VIA 1.4 V VIB 1V VID 0.4 V 0V -0.4 V RT1 = RT2 = RT VOZ tPHL tPLH 100% 0V 80% VOY - VOZ 20% tf 0% tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.25 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS OUTPUT INPUT VCC VCC A VCC VCC B Y Z 7V 7V 7V 7V TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE 12 10 10 8 6 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 200 mV, RT = 50 Ω, VTT = 2.5 V 4 2 0 1000 8 6 VCC = 3.3 V, VIC = 1.2 V, VID = 200 mV, f = 750 MHz, RT = 50 Ω, VTT = 2.5 V 4 2 0 0 250 500 750 −40 1000 −20 0 20 40 60 80 900 VCC = 3.3 V, TA = 25°C, VIC = 1.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE PEAK-TO-PEAK JITTER vs FREQUENCY 30 625 600 575 25 tPHL 550 35 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, RT = 50 Ω, VTT = 2.5 V, Input = Clock tPLH 20 15 VID = 0.3 V 10 VID = 0.5 V 5 525 500 −40 −20 0 20 40 60 80 VID = 0.8 V 25 20 VID = 0.5 V 15 10 VID = 0.3 V 5 0 100 100 VCC = 3.3 V, TA = 25°C, VIC = 1.2 V, VID = 0.8 V RT = 50 Ω, VTT = 2.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 TYPICAL CHARACTERISTICS (continued) 1.5 Gbps 223-1 PRBS 1.5 Gbps 223-1 PRBS Vertical Scale = 500 mV/div Vertical Scale = 250 mV/div 750 MHz 750 MHz Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 50 Ω Horizontal Scale = 200 ps/div VCC = 3.3 V, TA = 25°C, VID = 200 mV, VIC = 1.2 V, VTT = 2.5 V, RT = 25 Ω Figure 19. Figure 20. 1.5 Gbps 223-1 PRBS 1.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 TYPICAL CHARACTERISTICS (continued) Power Supply 1 + 3.3 V - Power Supply 2 + VTT J3 DUT GND J2 EVM GND J1 VCC J4 J5 J6 100 Ω J7 50 Ω DUT Pattern Generator Matched Cables SMA to SMA 50 Ω Matched Cables SMA to SMA EVM Oscilloscope Figure 23.
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SN65CML100 www.ti.com SLLS547 – NOVEMBER 2002 APPLICATION INFORMATION For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. When VBB is used, decouple VBB via a 0.01-µF capacitor and limit the current sourcing or sinking to 0.4 mA. When not used, VBB should be left open. TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.) 50 Ω 3.3 V or 5 V 3.3 V SN65CML100 A ECL B 50 Ω 50 Ω 50 Ω VTT = VCC -2 V VTT Figure 24.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65CML100DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65CML100DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65CML100DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 SN65CML100DR SOIC D 8 2500 340.5 338.1 20.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.