Datasheet

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1 8

2 7

3 6

4 5

GND

LVTTL

LVPECL

SN65EPT22

www.ti.com

SLLS926A –DECEMBER 2008–REVISED NOVEMBER 2010

3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer

Check for Samples: SN65EPT22

FEATURES

APPLICATIONS

• Data and Clock Transmission Over Backplane

• Dual 3.3V LVTTL to LVPECL Buffer

• Signaling Level Conversion

• Operating Range

– LVPECL V

= 3.0 V to 3.6 V With

DESCRIPTION

GND = 0 V

The SN65EPT22 is a low power dual LVTTL to

• Support for Clock Frequencies to 2.0 GHz (typ)

LVPECL translator device. The device includes

• 420 ps Typical Propagation Delay

circuitry to maintain known logic HIGH level when

• Deterministic HIGH Output Value for Open

inputs are in open condition. The SN65EPT22 is

Input Conditions

housed in an industry standard SOIC-8 package and

is also available in TSSOP-8 package option.

• Built-in Temperature Compensation

• Drop in Compatible to MC100ELT23

• PNP Single Ended Inputs for Minimal Loading

PINOUT ASSIGNMENT

Table 1. Pin Description

PIN FUNCTION

, D

LVTTL data inputs

, Q

LVPECL outputs

Positive supply

GND Ground

ORDERING INFORMATION

(1)

PART NUMBER PART MARKING PACKAGE LEAD FINISH

SN65EPT22D EPT22 SOIC NiPdAu

SN65EPT22DGK EPT22 SOIC-TSSOP NiPdAu

(1) Leaded device options not initially available. Contact sales representative for further details.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (12 pages)

PAGE 1
SN65EPT22 www.ti.com SLLS926A – DECEMBER 2008 – REVISED NOVEMBER 2010 3.3 V Dual LVTTL/LVCMOS to Differential LVPECL Buffer Check for Samples: SN65EPT22 FEATURES APPLICATIONS • • • • 1 • • • • • • Dual 3.3V LVTTL to LVPECL Buffer Operating Range – LVPECL VCC = 3.0 V to 3.6 V With GND = 0 V Support for Clock Frequencies to 2.
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SN65EPT22 SLLS926A – DECEMBER 2008 – REVISED NOVEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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SN65EPT22 www.ti.com SLLS926A – DECEMBER 2008 – REVISED NOVEMBER 2010 TTL INPUT DC CHARACTERISTICS (1) (VCC = 3.3 V, GND = 0, TA = –40°C to 85°C) CHARACTERISTIC CONDITION MIN TYP MAX UNIT IIH Input HIGH current VIN = 2.7 V IIHH Input HIGH current max VIN = VCC 100 mA IIL Input LOW current VIN = 0.5 V –0.
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SN65EPT22 SLLS926A – DECEMBER 2008 – REVISED NOVEMBER 2010 www.ti.com Typical Termination for Output Driver ZO = 50 W P P Receiver Driver N N ZO = 50 W 50 W 50 W VTT VTT = VCC - 2 V Figure 1. Termination for Output Driver 1.5 V 1.5 V IN OUT OUT tPLH tPHL Figure 2. Output Propagation Delay 80% 20% tr tf Figure 3.
PAGE 5
SN65EPT22 www.ti.com SLLS926A – DECEMBER 2008 – REVISED NOVEMBER 2010 1.5 V 1.5 V IN QO QO tPLH0 tPHL0 Q1 Q1 tPLH1 tPHL0 Device Skew = Higher [(tPLH1 - tPLH0), (tPHL1 - tPHL0)] Figure 4. Device Skew 1000 VCC = 3 V, GND = 0 V, Vswing = 0.8 V - 2 V 900 Output Amplitude - mV 800 TA = -40°C 700 TA = 25°C 600 500 TA = 85°C 400 300 200 100 0 0 500 1000 1500 f - Frequency - MHz 2000 2500 Figure 5.
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SN65EPT22 SLLS926A – DECEMBER 2008 – REVISED NOVEMBER 2010 www.ti.com REVISION HISTORY Changes from Original (November 2010) to Revision A • 6 Page Changed SN65EPT22 to EPT22 (2 places) in Ordering Information Table under Part Marking column .............................
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65EPT22DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65EPT22DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65EPT22DGKR VSSOP DGK 8 2500 367.0 367.0 35.0 SN65EPT22DR SOIC D 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.