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GND

LVPECL

LVTTL

SN65EPT23

www.ti.com

SLLS969A – NOVEMBER 2009– REVISED JANUARY 2011

3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator

Check for Samples: SN65EPT23

FEATURES

PINOUT ASSIGNMENT

• Dual 3.3 V Differential LVPECL/LVDS to

LVTTL/LVCMOS Buffer Translator

• 24 mA LVTTL Ouputs

• Operating Range

– V

= 3.0 V to 3.6 V

– GND = 0 V

• Support for Clock Frequencies > 300 MHz

• 2.0 ns Typical Propagation Delay

• Built-in Temperature Compensation

• Drop in Compatible to MC100EPT23

APPLICATIONS

• Data and Clock Transmission Over Backplane

Table 1. Pin Description

• Signaling Level Conversion for Clock or Data

PIN FUNCTION

, Q

LVTTL/LVCMOS Outputs

DESCRIPTION

, D

Differential LVPECL/LVDS/CML Inputs

The SN65EPT23 is a low power dual LVPECL/LVDS

Positive Supply

to LVTTL/LVCMOS translator device. The device

includes circuitry to maintain inputs at Vcc/2 when left GND Ground

open. The SN65EPT23 is housed in an industry

standard SOIC-8 package and is also available in

TSSOP-8 option.

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ORDERING INFORMATION

(1)

PART NUMBER PART MARKING PACKAGE LEAD FINISH

SN65EPT23D/DR EPT23 SOIC NiPdAu

SN65EPT23DGK/DGKR SSTI MSOP NiPdAu

(1) Leaded device option not initially available; contact TI sales representative for further information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator Check for Samples: SN65EPT23 FEATURES 1 • • • • • • • Dual 3.3 V Differential LVPECL/LVDS to LVTTL/LVCMOS Buffer Translator 24 mA LVTTL Ouputs Operating Range – VCC = 3.0 V to 3.6 V – GND = 0 V Support for Clock Frequencies > 300 MHz 2.
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SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com LVTTL OUTPUT DC CHARACTERISTICS (1) (VCC = 3.3 V; GND = 0 V, TA = -40C to 85C) (2) PARAMETER Output short circuit current VOH Output high voltage (3) IOH = –3.0 mA VOL Output low voltage IOL = 24 mA (2) (3) MIN 25°C TYP MAX –180 –140 IOS (1) –40°C CONDITION –50 MIN 85°C TYP MAX -180 –144 2.4 –50 MIN TYP MAX –180 –148 –50 2.4 2.4 0.5 UNIT mA V 0.5 0.
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SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com 5 VCC = 3°C Voltage - V 4 VOH @ -40°C 3 VOH @ 25°C 2 VOH @ 85°C VOL @ -40°C VOL @ 25°C 1 VOL @ 85°C 0 0 50 100 150 200 250 300 350 400 450 500 f - Frequency - MHz Figure 1. Maximum Switching Frequency VCC = 3.0 V 5 VCC = 3.3°C 4 Voltage - V VOH @ -40°C VOH @ 25°C 3 VOH @ 85°C 2 VOL @ -40°C VOL @ 25°C 1 0 0 VOL @ 85°C 50 100 150 200 250 300 350 400 450 500 f - Frequency - MHz Figure 2.
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SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com 5 VCC = 3.6°C 4 VOH @ -40°C Voltage - V VOH @ 25°C VOH @ 85°C 3 2 VOL @ -40°C VOL @ 25°C 1 VOL @ 85°C 0 0 50 100 150 200 250 300 350 400 450 500 f - Frequency - MHz Figure 3. Maximum Switching Frequency VCC = 3.6 V Typical Output Loading Used for Device Evaluation Application TTL Receiver Characteristic Test RL *CL *CL Includes Fixture Capacitance AC TEST LOAD GND Figure 4.
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SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com IN IN 1.5 V 1.5 V OUT tPLH tPHL Figure 6. Output Propagation Delay D VPP(min) VPP(max) D Figure 7.
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SN65EPT23 SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com REVISION HISTORY Changes from Original (November 2009) to Revision A • Page Deleted last row from the Pin Description Table (EP) ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65EPT23DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65EPT23DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65EPT23DGKR VSSOP DGK 8 2500 367.0 367.0 35.0 SN65EPT23DR SOIC D 8 2500 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.