Datasheet

1
FEATURES
DESCRIPTION
APPLICATIONS
V
ID
0 V
-0.05 V
0.05 V 0.10 V
-0.10 V -0.15 V -0.20 V
0.15 V 0.20 V
V
IT+
(T Y P )
V (T Y P )
RecevierOutputHigh
ReceiverOutputLow
IT
–
D
Z
Y
6
5
3
DP (TOP VIEW)ACKAGE
R
B
A
7
8
2
1
2
3
4
8
7
6
5
R
D
V
CC
B
A
Z
Y
GND
SN65HVD179
www.ti.com .................................................................................................................................................... SLLS668C – FEBRUARY 2006 – REVISED JULY 2008
5-V FULL-DUPLEX RS-485/RS-422 DRIVER AND BALANCED RECEIVER
• Designed for INTERBUS Applications
• Balanced Receiver Thresholds
The SN65HVD179 is a differential line driver and
differential-input line receiver that operates with a 5-V
• 1/2 Unit-Load (up to 64 nodes on the bus)
power supply. Each driver and receiver has separate
• Bus-Pin ESD Protection 15 kV HBM
input and output pins for full-duplex bus
• Bus-Fault Protection of – 7V to 12V
communication designs. They are designed for
balanced transmission lines and interoperation with
• Thermal Shutdown Protection
ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and
• Power-Up/Down Glitch-free Bus Inputs and
ISO 8482:1993 standard-compliant devices.
Outputs
The differential bus driver and receiver are monolithic,
• Designed for RS-422 and RS-485 Networks
integrated circuits designed for full-duplex
bi-directional data communication on multipoint
bus-transmission lines at signaling rates
(1)
up to 25
• Digital Motor Control
Mbps. The SN65HVD179 is fully enabled with no
• Utility Meters external enabling pins.
• Chassis-to-Chassis Interconnections
The 1/2 unit load receiver has a high receiver input
• Electronic Security Stations
resistance. This results in lower bus leakage currents
over the common-mode voltage range, and reduces
• Industrial, Process, and Building Automation
the total amount of current that a 485 driver is forced
• Point-of-Sale (POS) Terminals and Networks
to source or sink when transmitting.
• DTE/DCE Interfaces
The balanced differential receiver input threshold
makes the SN65HVD179 fully compatible with
fieldbus requirements that define an external failsafe
structure.
(1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
BALANCED RECEIVER INPUT THRESHOLDS SN65HVD179
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.