SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 3.3-V CAN TRANSCEIVERS D Thermal Shutdown Protection D Open-Circuit Fail-Safe Design FEATURES D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D D D D MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Operates With a 3.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 DESCRIPTION The SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers, or with equivalent devices. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 Function Tables DRIVER (SN65HVD230Q, SN65HVD231Q) OUTPUTS INPUT D RS CANH L V(Rs) < 1.2 12V H Open X BUS STATE CANL H L Dominant Z Z Recessive Z Z Recessive X V(Rs) > 0.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 Function Tables (Continued) TRANSCEIVER MODES (SN65HVD230Q, SN65HVD231Q) OPERATING MODE V(Rs) V(RS) > 0.75 VCC Standby 10 kΩ to 100 kΩ to ground Slope control V(RS) < 1 V High speed (no slope control) Terminal Functions SN65HVD230Q, SN65HVD231Q TERMINAL NAME DESCRIPTION NO.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 equivalent input and output schematic diagrams CANH and CANL Inputs D Input VCC VCC 110 kΩ 16 V 9 kΩ 100 kΩ 45 kΩ Input 1 kΩ Input 20 V 9 kΩ 9V CANH and CANL Outputs R Output VCC VCC 16 V 5Ω Output Output 9V 20 V www.ti.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Voltage range at any bus terminal (CANH or CANL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 driver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER VOH Dominant VI = 0 V, See Figure 1 and Figure 3 CANH CANH Recessive VI = 3 V, See Figure 1 and Figure 3 Bus output voltage VOL VOD(D) Dominant Differential output voltage VOD(R) Recessive MIN TYP† MAX 2.45 VCC CANL 0.5 1.25 V 2.3 CANL UNIT 2.3 VI = 0 V, See Figure 1 1.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 driver switching characteristics at TA = 25°C (unless otherwise noted) SN65HVD232Q PARAMETER TEST CONDITIONS MIN TYP MAX 35 85 UNIT ns 70 120 ns tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tP(HL) − tP(LH)|) tr Differential output signal rise time 25 50 100 ns tf Differential output signal fall time 40 55 80 ns
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 device control-pin characteristics over recommended operating conditions (unless otherwise noted) PARAMETER t(WAKE) TEST CONDITIONS SN65HVD230Q wake-up time from standby mode with RS MIN See Figure 8 TYP† MAX UNIT 0.55 1.5 µS 3 µS SN65HVD231Q wake-up time from sleep mode with RS † −5 µA < I(Vref) < 5 µA 0.45 VCC 0.55 VCC 0.4 VCC 0.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION RL = 60 Ω Signal Generator (see Note A) CL = 50 pF (see Note B) VO 50 Ω RS = 0 Ω to 100 kΩ for SN65HVD230Q and SN65HVD231Q N/A for SN65HVD232Q 3V Input 1.5 V 0V tP(LH) tP(HL) VOD(D) 90% 0.9 V Output 0.5 V 10% tr VOD(R) tf NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, Zo = 50 Ω.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION Output Signal Generator (see Note A) 50 Ω 1.5 V CL = 15 pF (see Note B) 2.9 V Input 2.2 V 1.5 V tP(LH) tP(HL) VOH 90% Output 1.3 V 10% tr VOL tf NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, Zo = 50 Ω. B. CL includes probe and jig capacitance. Figure 6.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION Table 1. Receiver Characteristics Over Common Mode With V(RS) at 1.2 V VIC VID VCANH VCANL R OUTPUT −2 V 900 mV −1.55 V −2.45 V L 7V 900 mV 8.45 V 6.55 V L 1V 6V 4V −2 V L 4V 6V 7V 1V L −2 V 500 mV −1.75 V −2.25 V H 7V 500 mV 7.25 V 6.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS LOGIC INPUT CURRENT (D PIN) vs INPUT VOLTAGE 33 0 32 −2 I I(L) − Logic Input Current − µ A I CC − Supply Current (RMS) − mA SUPPLY CURRENT (RMS) vs FREQUENCY 31 30 29 28 27 26 25 −4 −6 −8 −10 −12 −14 0 250 500 −16 750 1000 1250 1500 1750 2000 f − Frequency − kbps 0 1.1 1.6 2.1 2.6 3.1 3.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS DRIVER HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE DOMINANT VOLTAGE (VOD) vs FREE-AIR TEMPERATURE 3 VCC = 3.6 V 100 2.5 VOD− Dominant Voltage − V I OH − Driver High-Level Output Current − mA 120 80 60 40 VCC = 3 V 2 1.5 1 0.5 20 0 VCC = 3.3 V 0 0.5 1 1.5 2 2.5 3 0 3.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 55 RS = 0 VCC = 3 V 50 45 40 VCC = 3.3 V 35 VCC = 3.6 V 30 25 20 15 10 −55 −40 0 25 70 85 125 t PHL− Driver High-to-Low Propagation Delay Time − ns t PLH − Driver Low-to-High Propagation Delay Time − ns TYPICAL CHARACTERISTICS DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 90 RS = 0 VCC = 3.6 V 85 80 75 VCC = 3.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 800 RS = 100 kΩ 700 VCC = 3 V 600 VCC = 3.3 V 500 VCC = 3.6 V 400 300 200 100 0 −55 −40 0 25 70 85 125 DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PHL− Driver High-to-Low Propagation Delay Time − ns t PLH − Driver Low-to-High Propagation Delay Time − ns TYPICAL CHARACTERISTICS 1000 RS = 100 kΩ VCC = 3.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS REFERENCE VOLTAGE vs REFERENCE CURRENT 3 V ref − Reference Voltage − V 2.5 2 VCC = 3.6 V 1.5 VCC = 3 V 1 0.5 0 −50 −5 5 50 Iref − Reference Current − µA Figure 25 APPLICATION INFORMATION This application provides information concerning the implementation of the physical medium attachment layer in a CAN network according to the ISO 11898 standard.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION ISO 11898 Specification Implementation Application Specific Layer TMS320Lx2403/6/7 3.3-V DSP Logic Link Control Data-Link Layer Embedded Medium Access Control CAN Controller Physical Signaling Physical Layer Physical Medium Attachment SN65HVD230 Medium Dependant Interface CAN Bus−Line Figure 26.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION Electronic Control Unit (ECU) TMS320Lx2403/6/7 CAN-Controller CANTX/IOPC6 CANRX/IOPC7 D R SN65HVD230 CANH CANL CAN Bus Line Figure 27. Details of a Typical CAN Node ECU 1 ECU 2 ECU n CANH 120 Ω CAN Bus Line 120 Ω CANL Figure 28. Typical CAN Network The SN65HVD230Q/231Q/232Q 3.3-V CAN transceivers provide the interface between the 3.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION features of the SN65HVD230Q, SN65HVD231Q, and SN65HVD232Q (continued) The bus pins are also maintained in a high-impedance state during low VCC conditions to ensure glitch-free power-up and power-down bus protection for hot-plugging applications. This high-impedance condition also means that an unpowered node will not disturb the bus.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION high-speed mode (continued) 1 Mbps Driver Output NRZ Data 1 Figure 30. Typical SN65HVD230Q High-Speed Mode Output Waveform Into a 60-Ω Load slope-control mode Electromagnetic compatibility is essential in many applications using unshielded bus cable to reduce system cost.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION DRIVER OUTPUT SIGNAL SLOPE vs SLOPE CONTROL RESISTANCE Driver Output Signal Slope − V/µs 25 20 15 10 5 0 0 10 4.7 20 30 40 50 33 60 47 70 6.8 10 15 22 Slope Control Resistance − kΩ 80 68 90 100 Figure 32. SN65HVD230Q Driver Output Signal Slope vs Slope Control Resistance Value RS = 0 Ω RS = 10 kΩ RS = 100 kΩ Figure 33.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION standby mode (listen only mode) of the SN65HVD230Q If a logic high (> 0.75 VCC) is applied to RS (pin 8) in Figures 29 and 31, the circuit of the SN65HVD230Q enters a low-current, listen only standby mode during which the driver is switched off and the receiver remains active. In this listen only state, the transceiver is completely passive to the bus.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION Figure 34. 70.7-ns Loop Delay Through the SN65HVD230Q With RS = 0 24 www.ti.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION interoperability with 5-V CAN systems It is essential that the 3.3-V SN65HVD230Q family performs seamlessly with 5-V transceivers because of the large number of 5-V devices installed. Figure 35 displays a test bus of a 3.3-V node with the SN65HVD230Q, and three 5-V nodes: one for each of TI’s SN65LBC031 and UC5350 transceivers, and one using a competitor X250 transceiver.
SN65HVD230Q-Q1 SN65HVD231Q-Q1 SN65HVD232Q-Q1 SGLS398A − APRIL 2002 − REVISED APRIL 2008 APPLICATION INFORMATION Driver Input CAN Bus Receiver Output Figure 36. SN65HVD230Q’s Input, CAN Bus, and X250’s RXD Output Waveforms Figure 36 displays the SN65HVD230Q’s input signal, the CAN bus, and the competitor X250’s receiver output waveforms. The input waveform from the Tektronix HFS-9003 Pattern Generator in Figure 35 to the SN65HVD230Q is a 250-kbps pulse for this test.
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