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FEATURES DESCRIPTION

APPLICATIONS

CANL

CANH

Vcc

GND

Vref

4 5

function diagram

(positive logic)

ref

CANH

CANL

SN65HVD251-Q1

SLLS788 – APRIL 2007

CAN TRANSCEIVER

• Qualified for Automotive Applications

The SN65HVD251 is intended for use in applications

employing the Controller Area Network (CAN) serial

• Drop-In Improved Replacement for the

communication physical layer in accordance with the

PCA82C250 and PCA82C251

ISO 11898 Standard. The SN65HVD251 provides

• Bus-Fault Protection of ± 36 V

differential transmit capability to the bus and

• Meets or Exceeds ISO 11898

differential receive capability to a CAN controller at

speeds up to 1 megabit per second (Mbps).

• Signaling Rates

(1)

up to 1 Mbps

• High Input Impedance Allows up to 120

Designed for operation in harsh environments, the

SN65HVD251 Nodes on a Bus

device features crosswire, overvoltage, and loss of

ground protection to ± 36 V. Also featured are

• Bus Pins ESD Protection Exceeds 9 kV (HBM)

overtemperature protection as well as –7-V to 12-V

• Unpowered Node Does Not Disturb the Bus

common-mode range, and tolerance to transients of

• Low-Current Standby Mode: 200 μ A Typical

± 200 V. The transceiver interfaces the single-ended

CAN controller with the differential CAN bus found in

• Thermal Shutdown Protection

industrial, building automation, and automotive

• Glitch-Free Power-Up and Power-Down Bus

applications.

Protection for Hot Plugging

Rs, pin 8, selects one of three different modes of

• DeviceNet™ Vendor ID #806

operation: high-speed, slope control, or low-power

(1)

The signaling rate of a line is the number of voltage

mode. The high-speed mode of operation is selected

transitions that are made per second expressed in bps (bits

by connecting pin 8 to ground, allowing the

per second).

transmitter output transistors to switch as fast as

possible with no limitation on the rise and fall slope.

The rise and fall slope can be adjusted by

• CAN Data Buses

connecting a resistor to ground at pin 8; the slope is

• Industrial Automation

proportional to the pin's output current. Slope control

with an external resistor value of 10 k Ω gives

– DeviceNet Data Buses

~15 V/ μ s slew rate; 100 k Ω gives ~2 V/ μ s slew rate.

– Smart Distributed Systems (SDS™)

If a high logic level is applied to the Rs pin 8, the

• SAE J1939 Standard Data Bus Interface

device enters a low-current standby mode where the

• NMEA 2000 Standard Data Bus Interface

driver is switched off and the receiver remains active.

• ISO 11783 Standard Data Bus Interface

The local protocol controller returns the device to the

normal mode when it transmits to the bus.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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SN65HVD251-Q1 www.ti.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 THERMAL CHARACTERISTICS PARAMETER TEST CONDITIONS VALUE MIN TYP UNIT MAX θJB Junction-to-board thermal resistance 78.7 °C/W θJC Junction-to-case thermal resistance 44.6 °C/W PD TSD Device power dissipation VCC = 5 V, TJ = 27°C, RL = 60 Ω, RS at 0 V, Input to D a 500-kHz 50% duty cycle square wave 97.7 mW VCC = 5.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 2.75 3.5 4.5 VO(D) Bus output voltage (Dominant) CANH VO(R) Bus output voltage (Recessive) CANH VOD(D) Differential output voltage (Dominant) Figure 1, D at 0 V, Rs at 0 V VOD(D) Differential output voltage (Dominant) Figure 2 and Figure 3, D at 0 V, Rs at 0 V 1.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys Hysteresis voltage (VIT+ – VIT–) VOH High-level output voltage Figure 6, IO = –4 mA VOL Low-level output voltage Figure 6, IO = 4 mA MIN TYP 750 Rs at 0 V, (See Table 1) 500 0.8 VCC V 0.
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SN65HVD251-Q1 www.ti.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 PARAMETER MEASUREMENT INFORMATION IO(CANH) VO(CANH) D VOD II IIRs Rs VI 60 W + 1% + VO(CANH) + VO(CANL) 2 VOC IO(CANL) VI(Rs) _ VO(CANL) Figure 1. Driver Voltage, Current, and Test Definition Dominant Recessive 93.5 V VO(CANH) 92.5 V 91.5 V VO(CANL) Figure 2. Bus Logic State Voltage Definitions CANH VI D VOD 330 W 1% 60 W 1% + _ RS CANL –7 V VTEST 12 V 330 W 1% Figure 3.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 PARAMETER MEASUREMENT INFORMATION (continued) CANH D VI RL = 60 +1% + VI(Rs) _ Rs (see Note A) CL = 50 pF +20% (see Note B) VO CANH VCC VCC/2 VI VCC/2 0V tPHL tPLH 0.9V VO 90% 0.5V 10% tr VO(D) VO(R) tf Figure 4. Driver Test Circuit and Voltage Waveforms CANH R VI(CANH) VI(CANH) + VI(CANL) VIC = 2 VI(CANL) IO VID VO CANL Figure 5. Receiver Voltage and Current Definitions CANH R VI CANL (see Note A) 1.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 PARAMETER MEASUREMENT INFORMATION (continued) CANH R CANL 100 W Pulse Generator 15 ms Duration 1% Duty Cycle tr, tr 3 100 ns D at 0 V or VCC RS at 0 V or VCC A. This test is conducted to test survivability only. Data stability at the R output is not specified. Figure 7. Test Circuit, Transient Overvoltage Test Table 1. Receiver Characteristics Over Common Mode Voltage MEASURED OUTPUT VCANH INPUT VCANL |VID| R 12 V 11.1 V 900 mV L –6.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 CANH 27 W 1% D VI CANL 27 W 1% VOC RS 50 pF 20% VOC(PP) VOC A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. Figure 9. Peak-to-Peak Common Mode Output Voltage DUT CANH VI D 60 W + 1% 10 kW or 100 kW + 5% _ RS CANL VRs + R + VO _ 15 pF + 20% VCC 50% D Input 0V tLoop2 tLoop1 VOH 0.7 Vcc R Output 0.3 Vcc VOL Figure 10.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 IOS 0 V or VCC CANH D CANL Rs Vin –7 V or 12 V JIOS(SS)J JIOS(P)J 15 s 0V 12 V Vin 0V 10 ms or 0V Vin –7 V Figure 11. Driver Short-Circuit Test CANH R VI (see Note A) CANL CL = 15 pF 1.5 V VO (see Note B) 3.5 V 2.4 V VI 1.5 V tp(sb) VOH VO 0.3 VCC VOL A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 DEVICE INFORMATION 5V R2+1% R1+1% CANH + R VID – CANL Vac R1+1% VI R2+1% VID R1 R2 500 mV 50 W 450 W 900 mV 50 W 227 W 12 V VI –7 V A. All input pulses are supplied by a generator having the following characteristics: f < 1.5 MHz, TA = 25°C, VCC = 5 V. Figure 13. Common-Mode Input Voltage Rejection Test FUNCTION TABLES Table 2. DRIVER INPUTS D OUTPUTS Voltage at Rs, VRs CANH BUS STATE CANL L VRs < 1.2 V H L Dominant H VRs < 1.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 R Output D Input Vcc Vcc 100 kW 1 kW 15 W Input Output 9V 9V CANH Input CANL Input Vcc 110 kW Vcc 110 kW 9 kW 45 kW 9 kW 45 kW Input Input 40 V 9 kW 40 V CANH and CANL Outputs 9 kW Rs Input Vcc Vcc Output 40 V + Input Figure 14.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 TYPICAL CHARACTERISTICS tLOOP1 – LOOP TIME vs FREE-AIR TEMPERATURE tLOOP2 – LOOP TIME vs FREE-AIR TEMPERATURE SUPPLY CURRENT (RMS) vs SIGNALING RATE 150 33 72 tLOOP2 – Loop Time – ns VCC = 4.5 V VCC = 5 V 70 68 66 VCC = 5.5 V VCC = 5.5 V VCC = 5 V 140 135 130 VCC = 4.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 APPLICATION INFORMATION The basics of bus arbitration require that the receiver at the sending node designate the first bit as dominant or recessive after the initial wave of the first bit of a message travels to the most remote node on a network and back again. Typically, this sample is made at 75% of the bit width, and within this limitation, the maximum allowable signal distortion in a CAN network is determined by network electrical parameters.
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SN65HVD251-Q1 www.ti.com SLLS788 – APRIL 2007 An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 24, the differential signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all effects of systemic and random distortion, and displays the time during which a signal may be considered valid.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) SN65HVD251QDRQ1 ACTIVE Package Type Package Pins Package Drawing Qty SOIC D 8 2500 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-1-260C-UNLIM (4) -40 to 125 251Q1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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