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User's Guide

SLLU152–December 2012

SN65HVD62 AISG On-Off Keying Modem Evaluation

Module (EVM)

ABSTRACT?

Contents

1 Introduction .................................................................................................................. 2

1.1 Overview ............................................................................................................ 2

1.2 SN65HVD62EVM Kit Contents ................................................................................... 2

2 EVM Description ............................................................................................................ 2

2.1 EVM Schematic .................................................................................................... 3

2.2 EVM Configuration: Jumpers and Test Points ................................................................. 6

3 EVM Setup and Operation ................................................................................................. 8

3.1 Equipment ........................................................................................................... 8

3.2 Standalone Evaluation ............................................................................................ 8

3.3 System Evaluation ................................................................................................ 12

3.4 External Clock Input .............................................................................................. 13

3.5 Standby Mode ..................................................................................................... 13

4 Bill Of Materials (BOM) ................................................................................................... 14

5 SN65HVD62EVM Layout ................................................................................................. 15

List of Figures

1 SN65HVD62 Pinout......................................................................................................... 2

2 SN65HVD62 EVM .......................................................................................................... 3

3 SN65HVD62EVM Schematics ............................................................................................ 4

4 Time Domain Waveforms for 115.2kbps Transmission................................................................ 9

5 Emission Spectrum for 115.2kbps Transmission: up to 30MHz ...................................................... 9

6 Emission Spectrum for 115.2kbps Transmission: 30MHz to 400MHz.............................................. 10

7 Rx Channel Evaluation: 160mVpp input at RXIN ..................................................................... 11

8 Rx Channel Evaluation: 80mVpp input at RXIN....................................................................... 11

9 EVM System Evaluation Block Diagram ............................................................................... 12

10 System Evaluation with U1 as Transmitter and U2 as Receiver at 115.2kbps.................................... 13

11 SN65HVD62EVM Top Layer Routing................................................................................... 15

12 SN65HVD62EVM Bottom Layer Routing............................................................................... 16

List of Tables

1 SN65HVD62EVM Description ............................................................................................. 5

2 Jumper Settings Description............................................................................................... 6

3 Test Point Description ...................................................................................................... 7

4 Data Rate Settings.......................................................................................................... 8

5 SN65HVD62EVM Bill Of Materials...................................................................................... 14

SLLU152–December 2012 SN65HVD62 AISG On-Off Keying Modem Evaluation Module (EVM)

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Summary of content (21 pages)

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User's Guide SLLU152 – December 2012 SN65HVD62 AISG On-Off Keying Modem Evaluation Module (EVM) ABSTRACT? 1 2 3 4 5 Contents Introduction .................................................................................................................. 2 1.1 Overview ............................................................................................................ 2 1.2 SN65HVD62EVM Kit Contents ...................................................................................
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Introduction 1 www.ti.com Introduction This user’s guide details the evaluation module (EVM) operation of factory installed SN65HVD62 AISG On Off Keying Coax Modem Transceivers. The EVM may be configured to evaluate one SN65HVD62 IC in a stand-alone configuration or to hook up two EVMS in a system scenario with one acting as a transmitter while the other acts as the receiver and vice-versa. 1.
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EVM Description www.ti.com Figure 2. SN65HVD62 EVM The two edge mounted SMA connectors, J1 and J3, are the coax interface to the SN65HVD62 devices, U1 and U2 respectively. The two devices have their own independent ground planes which may be shorted together using jumpers E3, E4, and JU14 to provide a common ground plane for the entire EVM. Jumper JU13 can be shorted to provide a communication path between the two SN65HVD62 devices at the coax interface without requiring an external cable. 2.
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EVM Description www.ti.com Figure 3.
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EVM Description www.ti.com The various EVM components and their functions are described in Table 1. Table 1. SN65HVD62EVM Description Label Description U1, U2 SN65HVD62 AISG Device TP5, TP13 Test point to access SYNCOUT pin of U1 and U2, respectively JU15, JU16 Jumpers to pull-up SYNCOUT to VCC for U1, U2 respectively. Default: these jumpers are shorted.
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EVM Description 2.2 www.ti.com EVM Configuration: Jumpers and Test Points Table 2 summarizes the jumper settings. An asterisk (*) indicates the default setting of the jumpers. Table 2. Jumper Settings Description Jumper Shunt Position Description Short* U1 VL pin connected to U1 VCC pin (single supply) Open U1 VLpin disconnected from U1 VCC pin Jumper settings for U1 JU1 JU2 1-2* 2-3 JU3 1-2 Direction Control Settings for U1. Default setting is for 115.2kbps data rate.
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EVM Description www.ti.com Table 3.
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EVM Setup and Operation 3 www.ti.com EVM Setup and Operation This section describes the EVM configuration(s) required to set-up the EVM for device evaluation. The EVM can be configured to evaluate one SN65HVD62 device individually or evaluate two of devices simultaneously, one device acting as the transmitter and the other as the receiver. Table 4 describes the jumper settings required for setting up U1 and U2 for various data rates during this evaluation. Table 4.
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EVM Setup and Operation www.ti.com 6. Connect the waveform-generator output between TP6 (TXIN) and TP2 (GND). 7. Connect the oscilloscope channel 1 to TP6 (TXIN). 8. Connect the oscilloscope channel 2 to TP17 (TXOUT). 9. Connect the oscilloscope channel 3 to JU4, pin2 (RES). 10. Example waveforms for a 115.2kbps setting are shown in Figure 4. Figure 4. Time Domain Waveforms for 115.2kbps Transmission 11. Now look at the output spectrum of the transmitter by connecting a spectrum analyzer to J1.
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EVM Setup and Operation www.ti.com 12. A spectrum for higher frequency ranges can be checked. If the signal is captured then the dynamic range of the spectrum analyzer will limit the noise floor performance. To improve the measurement a high pass filter has been used to remove the signal content while leaving the emissions content unaffected in the emission spectrum plot from 30MHz to 400MHz shown in Figure 6. Figure 6. Emission Spectrum for 115.2kbps Transmission: 30MHz to 400MHz 13.
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EVM Setup and Operation www.ti.com Figure 7. Rx Channel Evaluation: 160mVpp input at RXIN 11. Change the input amplitude to 80mVpp. 12. Example waveforms with an 80mVpp sine wave input at J1 are shown in Figure 8. RXOUT is high and DIR is low indicating the device is not in Receive mode. Figure 8.
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EVM Setup and Operation 3.3 www.ti.com System Evaluation This section covers the board configuration required to evaluate U1 and U2 in communication with one another. Figure 9 illustrates the device configuration in this mode. Figure 9. EVM System Evaluation Block Diagram 1. Retain the default jumper settings as described in Table 2. 2. Set the DC power supply to source 5V with 80mA current limit and connect it between TP1 (U1_VCC) and TP2 (GND). 3.
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EVM Setup and Operation www.ti.com Figure 10. System Evaluation with U1 as Transmitter and U2 as Receiver at 115.2kbps 3.4 External Clock Input The default setting for the clock source at the XTAL1 pin of U1 and U2 is the on-board crystal, Y1 and Y2 respectively. The SN65HVD62EVM also provides an option to use an external clock source on the XTAL1 pin. The following steps must be followed to enable this option for U1. Corresponding jumpers need to be used to enable this option for U2. 1.
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Bill Of Materials (BOM) 4 www.ti.com Bill Of Materials (BOM) Table 5 shows the parts list for the SN65HVD62EVM. Table 5. SN65HVD62EVM Bill Of Materials ITEM QTY REFERENCE DESIGNATOR PART DESCRIPTION MFG 1 4 C1,C2,C10,C11 CAPACITOR,SMT,0805,CERAMIC,10u F,10V,10%,X5R,LOW ESR TAIYO YUDEN/ANY 2 4 C3,C4,C12,C13 CAPACITOR,SMT,0603,CERAMIC,0.1u AVX/ANY F,16V,10%,X7R 3 2 C5,C14 CAPACITOR,SMT,0603,CERAMIC,1.
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SN65HVD62EVM Layout www.ti.com 5 SN65HVD62EVM Layout Figure 11 shows the top layer routing of the SN65HVD62EVM. Figure 11. SN65HVD62EVM Top Layer Routing Figure 12 shows the bottom layer routing and ground planes.
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SN65HVD62EVM Layout www.ti.com Figure 12.
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EVALUATION BOARD/KIT/MODULE (EVM) ADDITIONAL TERMS Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions: The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods.
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FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
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【Important Notice for Users of this Product in Japan】】 This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product: 1. 2. 3. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.
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EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMERS For Feasibility Evaluation Only, in Laboratory/Development Environments. Unless otherwise indicated, this EVM is not a finished electrical equipment and not intended for consumer use.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.