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    

SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Designed for TIA/EIA-485, TIA/EIA-422,

and ISO 8482 Applications

D Signaling Rates

†

up to 30 Mbps

D Propagation Delay Times <11 ns

D Low Standby Power Consumption

1.5 mA Max

D Output ESD Protection 12 kV

D Driver Positive- and Negative-Current

Limiting

D Power-Up and Power-Down Glitch-Free for

Live Insertion Applications

D Thermal Shutdown Protection

D Industry Standard Pin-Out, Compatible

With SN75172, AM26LS31, DS96172,

LTC486, and MAX3045

description

The SN65LBC172A and SN75LBC172A are quadruple differential line drivers with 3-state outputs, designed

for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications.

GND

N PACKAGE

(TOP VIEW)

logic diagram (positive logic)

GND

16-DW PACKAGE

(TOP VIEW)

GND

20-DW PACKAGE

(TOP VIEW)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS is a trademark of Texas Instruments.

†

The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

Summary of content (21 pages)

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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 D Designed for TIA/EIA-485, TIA/EIA-422, D Driver Positive- and Negative-Current and ISO 8482 Applications Signaling Rates† up to 30 Mbps Propagation Delay Times <11 ns Low Standby Power Consumption 1.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 description (continued) These devices are optimized for balanced multipoint bus transmission at signalling rates up to 30 million bits per second. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 equivalent input and output schematic diagrams Y or Z Output A, G, or G Input VCC VCC 16 V 20 V 100 kΩ 16 V 1 kΩ Input Output 16 V 9V 17 V 16 V absolute maximum ratings† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Output voltage range, VO, at any bus (steady state) . . . . . . . . . . . . . .
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 recommended operating conditions Supply voltage, VCC Voltage at any bus terminal High-level input voltage, VIH Low-level input voltage, VIL Y, Z A, G, G Output current Operating free-air temperature, TA MIN NOM MAX UNIT 4.75 5 5.25 V −7 12 V 2 0 VCC 0.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 switching characteristics over recommended operating conditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH tPHL Propagation delay time, low-to-high level output 5.5 8 11 ns Propagation delay time, high-to-low level output 5.5 8 11 ns tr tf Differential output voltage rise time 3 7.5 11 ns 3 7.5 11 ns tsk(p) tsk(o) Pulse skew |tPLH – tPHL| 0.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION IOY Y II A Z IOZ VOD VOY 54 Ω GND VI VOZ Figure 1. Test Circuit, VOD Without Common-Mode Loading 375 Ω Y A Input VOD 60 Ω Z VTEST = −7 V to 12 V 375 Ω VTEST VI Figure 2.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 Y A CL = 50 pF‡ VOD RL = 54 Ω Z Signal Generator† 50 Ω † PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω ‡ Includes probe and jig capacitance 3V 1.5 V Input 0V tPLH tPHL ≈ 1.5 V 90% 0V 10% Output tr ≈ −1.5 V tf Figure 4.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION Y S1 A 0 V or 3 V w Output Z Input Signal Generator† CL = 50 pF‡ G G 50 Ω 3V † PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω ‡ Includes probe and jig capacitance § 3-V if testing Y output, 0 V if testing Z output 3V 1.5 V Input 0V tPZH 0.5 V VOH 2.3 V 0V Output tPHZ Figure 5.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 PARAMETER MEASUREMENT INFORMATION 5V RL = 110 Ω Y S1 A 0 V or 3 V w Output Z Input Signal Generator† CL = 50 pF‡ G G 50 Ω 3V † PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50 Ω ‡ Includes probe and jig capacitance § 3-V if testing Y output, 0 V if testing Z output 3V 1.5 V Input 0V tPZL tPLZ 5V Output 2.3 V VOL 0.5 V Figure 6.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 Y IO VI Z VTEST Voltage Source VTEST = −7 V to 12 V Slew Rate ≤ 1.2 V/µs Figure 7. Test Circuit, Short-Circuit Output Current Y Z 100 Ω VTEST 0V Pulse Generator 15 µs Duration, 1% Duty Cycle 15 µs 1.5 ms Figure 8.
PAGE 11
SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS DIFFERENTIAL OUTPUT VOLTAGE vs OUTPUT CURRENT DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 2.5 3.5 VOD − Differential Output Voltage − V VOD − Differential Output Voltage − V 4 3 VCC = 5.25 V 2.5 VCC = 5 V 2 1.5 VCC = 4.75 V 1 0.5 0 0 20 40 60 80 IO − Output Current − mA VCC = 5.25 V 2 VCC = 5 V 1.5 VCC = 4.75 V 1 0.
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SLLS447C − OCTOBER 2000 − REVISED AUGUST 2008 TYPICAL CHARACTERISTICS RL = 54 Ω CL = 50 pF Figure 13. Eye Pattern, Pseudorandom Data at 30 Mbps APPLICATION INFORMATION TMS320F243 DSP (Controller) SN65LBC172A SN65LBC175A SPISIMO TMS320F241 DSP (Embedded Application) SPISIMO IOPA1 (Enable) SPISTE SPISTE IOPA1 IOPA2 SPICLK SPICLK IOPA0 (Handshake /Status) IOPA0 SPISOMI SPISOMI Figure 14.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LBC172A16DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 SN65LBC172ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN65LBC172ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LBC172A16DWR SOIC DW 16 2000 367.0 367.0 38.0 SN65LBC172ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN65LBC172ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN75LBC172A16DWR SOIC DW 16 2000 367.0 367.0 38.0 SN75LBC172ADWR SOIC DW 20 2000 367.0 367.0 45.0 SN75LBC172ADWR SOIC DW 20 2000 367.0 367.0 45.
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