Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers LVDS SSOP 28

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FEATURES DESCRIPTION

SYNC1

SYNC2

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

TCLK_R/F

TCLK

AGND

PWRDN

AGND

–

AGND

DEN

AGND

DGND

SN65LV1021

Serializer

AGND

RCLK_R/F

REFCLK

–

PWRDN

REN

RCLK

LOCK

AGND

DGND

OUT0

OUT1

OUT2

OUT3

OUT4

DGND

OUT5

OUT6

OUT7

OUT8

OUT9

SN65LV1212

Deserializer

SN65LV1021

SN65LV1212

SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005

10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER

• 100-Mbps to 400-Mbps Serial LVDS Data

The SN65LV1021 serializer and SN65LV1212

Payload Bandwidth at 10-MHz to 40-MHz

deserializer comprise a 10-bit serdes chipset

System Clock

designed to transmit and receive serial data over

LVDS differential backplanes at equivalent parallel

• Pin-Compatible Superset of NSM

word rates from 10 MHz to 40 MHz. Including

DS92LV1021/DS92LV1212

overhead, this translates into a serial data rate

• Chipset (Serializer/Deserializer) Power

between 120-Mbps and 480-Mbps payload-encoded

Consumption <350 mW (Typ) at 40 MHz

throughput.

• Synchronization Mode for Faster Lock

Upon power up, the chipset link can be initialized via

• Lock Indicator

a synchronization mode with internally generated

SYNC patterns, or the deserializer can be allowed to

• No External Components Required for PLL

synchronize to random data. By using the

• Low-Cost 28-Pin SSOP Package

synchronization mode, the deserializer establishes

• Industrial Temperature Qualified,

lock within specified, shorter time parameters.

= -40°C to 85°C

The device can be entered into a power-down state

• Programmable Edge Trigger on Clock

when no data transfer is required. Alternatively, a

(Rising or Falling Edge)

mode is available to place the output pins in the

• Flow-Through Pinout for Easy PCB Layout high-impedance state without losing PLL lock.

The SN65LV1021 and SN65LV1212 are

characterized for operation over ambient air

temperature of -40°C to 85°C.

ORDERING INFORMATION

DEVICE PART NUMBER

Serializer SN65LV1021DB

Deserializer SN65LV1212DB

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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SN65LV1021 SN65LV1212 www.ti.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 FUNCTIONAL DESCRIPTION (continued) When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low. When LOCK is low, the deserializer outputs represent incoming LVDS data.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 FUNCTIONAL DESCRIPTION (continued) DIN0 Held Low and DIN1 Held High Stop Bit Start Bit DIN0 Stop Bit Start Bit Stop Bit Start Bit Stop Bit Start Bit DIN1 DIN4 Held Low and DIN5 Held High Stop Bit Start Bit DIN4 DIN5 DIN8 Held Low and DIN9 Held High Stop Bit Start Bit DIN8 DIN9 Figure 1.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 FUNCTIONAL DESCRIPTION (continued) Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to the embedded clock and uses it to recover the serialized data. ROUTx data is valid when LOCK is low, otherwise ROUT0-ROUT9 is invalid. The ROUT0-ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be used is selected by the RCLK_R/F input.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 TERMINAL FUNCTIONS PIN NAME DESCRIPTION SYNC1, SYNC2 LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is asserted high for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC to GND -0.3 V to 4 V LVTTL input voltage -0.3 V to (VCC + 0.3 V) LVTTL output voltage -0.3 V to (VCC + 0.3 V) LVDS receiver input voltage -0.3 V to 3.9 V LVDS driver output voltage -0.3 V to 3.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 ELECTRICAL CHARACTERISTICS (continued) over recommended operating supply and temperature ranges (unless otherwise noted) PARAMETER IOZ High-impedance output current TEST CONDITIONS PWRDN or REN = 0.8 V, VOUT = 0 V or VCC MIN TYP MAX -10 ±1 10 350 400 1.1 1.
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SN65LV1021 SN65LV1212 www.ti.
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SN65LV1021 SN65LV1212 www.ti.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 10 pF tTLH(L) DO+ tTHL(L) RL 80% Vdiff 80% 20% 20% DO– 10 pF Vdiff = (DO+) – (DO–) Figure 4. Serializer LVDS Output Load and Transition Times Deserializer CMOS/TTL Output tTLH(C) tTHL(L) 80% 15 pF 80% 20% 20% Figure 5. Deserializer CMOS/TTL Output Load and Transition Times tt(CLK) TCLK tt(CLK) 90% 10% 3V 90% 10% 0V Figure 6. Serializer Input Clock Transition Time tTCP 1.5 V TCLK 1.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 Parasitic Package and Trace Capacitance 3V DEN 1.5 V 1.5 V 0V td(ZH) td(HZ) 13.5 Ω DO+ VOH 50% 50% 1.1 V 1.1 V DO– DO± 13.5 Ω DEN td(ZL) td(LZ) 1.1 V 50% 50% VOL Figure 8. Serializer High-Impedance-State Test Circuit and Timing PWRDN 2V 0.8 V td(HZ) or td(LZ) 1026 Cycles TCLK td(ZH) or td(ZL) t(PLD) DO± 3-State 1026 Cycles Output Active 3-State SYNC Pattern DEN = High tw(SP) SYNC 1.5 V 1.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 REN PWRDN TCLK tw(SP) SYNC1 or SYNC2 DO± DATA SYNC Pattern TCLK SYNC1 or SYNC2 tw(SP) Min. Timing Met DO± DATA SYNC Pattern Figure 10. SYNC Timing Delays DIN DIN0 – DIN9 SYMBOL N DIN0 – DIN9 SYMBOL N+1 td(S) TCLK Timing for TCLK_R/F = High Start Stop Start Bit D00 – D09 SYMBOL N–1 Bit Bit D00 – D09 SYMBOL N Stop Bit DO Figure 11.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 Start Bit D00 – D09 SYMBOL N Stop Start Bit Bit D00 – D09 SYMBOL N+1 Stop Start Bit Bit D00 – D09 SYMBOL N+2 Stop Bit RI 1.2 V 1V tDD RCLK Timing for TCLK_R/F = High ROUT ROUT0 – ROUT9 SYMBOL N–1 ROUT0 – ROUT9 SYMBOL N ROUT0 – ROUT9 SYMBOL N+1 Figure 12. Deserializer Delay tLow tHigh RCLK RCLK_R/F = Low tHigh tLow RCLK RCLK_R/F = High tROH tROS ROUT [9:0] 1.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 PWRDN 2V 0.8 V REFCLK 1.5 V tDSR1 DATA RI± Not Important td(ZHL) LOCK SYNC Patterns 3-State 3-State td(ZH) or td(ZL) ROUT[9:0] td(HZ) or td(LZ) 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State RCLK_R/F = Low REN Figure 15.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 3.6 V 3V VCC 0V PWRDN 0.8 V REFCLK tDSR2 DATA 1.2 V RI± Not Important 1V SYNC Patterns LOCK 3-State td(ZH) or td(ZL) ROUT[9:0] td(HZ) or td(LZ) 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State REN Figure 16. Deserilaizer PLL Lock Time From SyncPAT 1.
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SN65LV1021 SN65LV1212 www.ti.com SLLS526G – FEBRUARY 2002 – REVISED DECEMBER 2005 DO+ RL 10 DIN Parallel-to-Serial DO– > TCLK VOD = (DO+) – (DO–) Differential Output Signal Is Shown as (DO+) – (DO–) Figure 18.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LV1021DBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 SN65LV1212DBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LV1021DBR SSOP DB 28 2000 346.0 346.0 33.0 SN65LV1212DBR SSOP DB 28 2000 346.0 346.0 33.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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