Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - deserialisers LVTTL SSOP 28

SYNC1

SYNC2

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

TCLK_R/F

TCLK

AGND

PWRDN

AGND

−

AGND

DEN

AGND

DGND

DB Package

SN65LV1023A

Serializer

32 31 30 29 28 27 26 25

9 10 11 12 13 14 15 16

IN1

IN4

IN5

IN6

IN7

IN8

AGND

PWRDN

AGND

O+

O−

AGND

DEN

AGND

RHB Package

SN65LV1023A

Serializer

(Top View)

IN0

SYNC2

SYNC1

IN9

TCLK_R/F

TCLK

DGND

SN65LV1023A

SN65LV1224B

www.ti.com

SLLS621E –SEPTEMBER 2004–REVISED DECEMBER 2009

10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER

Check for Samples: SN65LV1023A SN65LV1224B

FEATURES

DESCRIPTION

• 100-Mbps to 660-Mbps Serial LVDS Data

Payload Bandwidth at 10-MHz to 66-MHz

The SN65LV1023A serializer and SN65LV1224B

System Clock

deserializer comprise a 10-bit serdes chipset

designed to transmit and receive serial data over

• Pin-Compatible Superset of

LVDS differential backplanes at equivalent parallel

DS92LV1023/DS92LV1224

word rates from 10 MHz to 66 MHz. Including

• Chipset (Serializer/Deserializer) Power

overhead, this translates into a serial data rate

Consumption <450 mW (Typ) at 66 MHz

between 120-Mbps and 792-Mbps payload encoded

• Synchronization Mode for Faster Lock

throughput.

• Lock Indicator

Upon power up, the chipset link can be initialized via

a synchronization mode with internally generated

• No External Components Required for PLL

SYNC patterns or the deserializer can be allowed to

• 28-Pin SSOP and Space Saving 5 × 5 mm QFN

synchronize to random data. By using the

Packages Available

synchronization mode, the deserializer establishes

• Industrial Temperature Qualified,

lock within specified, shorter time parameters.

= −40°C to 85°C

The device can be entered into a power-down state

• Programmable Edge Trigger on Clock

when no data transfer is required. Alternatively, a

• Flow-Through Pinout for Easy PCB Layout

mode is available to place the output pins in the

high-impedance state without losing PLL lock.

APPLICATIONS

The SN65LV1023A and SN65LV1224B are

• Wireless Base Station

characterized for operation over ambient air

• Backplane Interconnect

temperature of –40°C to 85°C.

• DSLAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

PAGE 1
SN65LV1023A SN65LV1224B www.ti.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 FUNCTIONAL DESCRIPTION The SN65LV1023A and SN65LV1224B are a 10-bit serializer/deserializer chipset designed to transmit data over differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 66 MHz. The chipset has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down mode, and high-impedance mode.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.com DIN0 Held Low and DIN1 Held High Stop Bit Start Bit DIN0 Stop Bit Start Bit Stop Bit Start Bit Stop Bit Start Bit DIN1 DIN4 Held Low and DIN5 Held High Stop Bit Start Bit DIN4 DIN5 DIN8 Held Low and DIN9 Held High Stop Bit Start Bit DIN8 DIN9 Figure 1. RMT Pattern Examples DATA TRANSMISSION MODE After initialization and synchronization, the serializer accepts parallel data from inputs DIN0–DIN9.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low, otherwise ROUT0–ROUT9 is invalid. The ROUT0−ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be used is selected by the RCLK_R/F input.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.com PIN FUNCTIONS PIN DB PACKAGE I/O RHB PACKAGE DESCRIPTION SERIALIZER 18, 20, 23, 25 17, 19, 22, 24 AGND Analog circuit ground (PLL and analog circuits) 17, 26 16, 25 AVCC Analog circuit power supply (PLL and analog circuits) 19 18 DEN LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serial data output.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT −0.3 V to 4 V VCC to GND LVTTL input voltage −0.3 V to (VCC + 0.3 V) LVTTL output voltage −0.3 V to (VCC + 0.3 V) LVDS receiver input voltage −0.3 V to 3.9 V LVDS driver output voltage −0.3 V to 3.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (1) VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V VCL Input clamp voltage IIN Input current, ICL = −18 mA (2) VIN = 0 V or 3.6 V –200 -0.86 –1.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 1000 900 800 VOD VOD IN - mV 700 600 500 400 300 200 100 0 0 20 40 60 80 100 120 140 Termination (RL) - W Figure 2. Typical VOD Curve SERIALIZER TIMING REQUIREMENTS FOR TCLK over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER MIN TYP MAX UNIT 15.15 T 100 ns Transmit clock high time 0.4T 0.5T 0.6T ns tTCIL Transmit clock low time 0.4T 0.5T 0.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 DESERIALIZER SWITCHING CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER t(RCP) Receiver out clock period tTLH(C) CMOS/TTL low-to-high transition time tTHL(C) CMOS/TTL high-to-low transition time td(D) Deserializer delay, See Figure 14 t(ROS) TEST CONDITIONS t(RCP) = t(TCP), See Figure 13 CL = 15 pF, CL = 15 pF, See Figure 7 Room temperature, 3.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.com TIMING DIAGRAMS AND TEST CIRCUITS TCLK ODD DIN EVEN DIN Figure 3. Worst-Case Serializer ICC Test Pattern SUPPLY CURRENT vs TCLK FREQUENCY 60 66 MHz, 48.88 mA ICC − Supply Current − mA 50 40 ICC 30 20 10 MHz, 14.732 mA 10 0 0 20 40 60 80 TCLK Frequency − MHz Figure 4.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 RCLK ODD ROUT EVEN ROUT Figure 5. Worst-Case Deserializer ICC Test Pattern 10 pF tTLH(L) DO+ RL tTHL(L) 80% Vdiff 80% 20% 20% DO− 10 pF Vdiff = (DO+) − (DO−) Figure 6. Serializer LVDS Output Load and Transition Times CMOS/TTL Output Deserializer tTHL(C) tTLH(C) 80% 15 pF 80% 20% 20% Figure 7.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.com tTCP 1.5 V TCLK 1.5 V 1.5 V For TCLK_R/F = Low th(DI) tsu(DI) DIN [9:0] 1.5 V Setup Hold 1.5 V Figure 9. Serializer Setup/Hold Times Parasitic Package and Trace Capacitance 3V DEN 1.5 V 1.5 V 0V td(ZH) td(HZ) VOH 13.5 Ω DO+ 50% 1.1 V DO− DO± 50% 1.1 V td(ZL) td(LZ) 13.5 Ω DEN 1.1 V 50% 50% VOL Figure 10. Serializer High-Impedance State Test Circuit and Timing PWRDN 2V 0.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 REN PWRDN TCLK tw(SP) SYNC1 or SYNC2 DO± DATA SYNC Pattern TCLK SYNC1 or SYNC2 tw(SP) Min. Timing Met DO± SYNC Pattern DATA Figure 12. SYNC Timing Delays DIN DIN0 − DIN9 SYMBOL N DIN0 − DIN9 SYMBOL N+1 td(S) TCLK Timing for TCLK_R/F = High Start D00 − D09 SYMBOL N−1 Bit Stop Start Bit Bit D00 − D09 SYMBOL N Stop Bit DO Figure 13.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 Start Bit www.ti.com Stop Start Bit Bit D00 − D09 SYMBOL N D00 − D09 SYMBOL N+1 Stop Start Bit Bit D00 − D09 SYMBOL N+2 Stop Bit RI 1.2 V 1V tDD RCLK Timing for TCLK_R/F = High ROUT ROUT0 − ROUT9 SYMBOL N−1 ROUT0 − ROUT9 SYMBOL N ROUT0 − ROUT9 SYMBOL N+1 Figure 14. Deserializer Delay tLow tHigh RCLK RCLK_R/F = Low tHigh tLow RCLK RCLK_R/F = High tROH tROS ROUT [9:0] 1.
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SN65LV1023A SN65LV1224B www.ti.com PWRDN SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 2V 0.8 V REFCLK 1.5 V t(DSR1) DATA RI± Not Important td(ZHL) LOCK SYNC Patterns 3-State 3-State td(ZH) or td(ZL) ROUT[9:0] td(HZ) or td(LZ) 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State RCLK_R/F = Low REN Figure 17.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.com 3.6 V 3V VCC 0V PWRDN 0.8 V REFCLK t(DSR2) DATA 1.2 V RI± Not Important 1V SYNC Patterns LOCK 3-State td(ZH) or td(ZL) ROUT[9:0] td(HZ) or td(LZ) 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State REN Figure 18. Deserializer PLL Lock Time From SyncPAT 1.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 DO+ RL 10 Parallel-to-Serial DIN DO− > TCLK VOD = (DO+) − (DO−) Differential Output Signal Is Shown as (DO+) − (DO−) Figure 20. VOD Diagram DEVICE STARTUP PROCEDURE It is recommended that the PWRDNB pin on both the SN65LV1023A and the SN65LV1224B device be held to a logic LOW level until after the power supplies have powered up to at least 3 V as shown in Figure 21. 3.0 V VDD PWRDNB Figure 21.
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SN65LV1023A SN65LV1224B SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 www.ti.com APPLICATION INFORMATION DIFFERENTIAL TRACES AND TERMINATION The performance of the SN65LV1023A/SN65LV1224B is affected by the characteristics of the transmission medium. Use controlled-impedance media and termination at the receiving end of the transmission line with the media’s characteristics impedance. Use balanced cables such as twisted pair or differential traces that are ran close together.
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SN65LV1023A SN65LV1224B www.ti.com SLLS621E – SEPTEMBER 2004 – REVISED DECEMBER 2009 ASIC ASIC ASIC ASIC 54 Ω 54 Ω Figure 24. Multiple Serializers and Deserializers on the Same Differential Bus SPACER REVISION HISTORY Changes from Original (September 2004) to Revision A Page • Changed Figure 17 ............................................................................................................................................................. 17 • Changed Figure 18 .....................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LV1023ADBR SSOP DB 28 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 SN65LV1023ARHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 SN65LV1023ARHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 17-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LV1023ADBR SN65LV1023ARHBR SSOP DB 28 2000 367.0 367.0 38.0 VQFN RHB 32 3000 338.1 338.1 20.6 SN65LV1023ARHBT VQFN RHB 32 250 210.0 185.0 35.0 SN65LV1224BDBR SSOP DB 28 2000 367.0 367.0 38.0 SN65LV1224BRHBR VQFN RHB 32 3000 338.1 338.1 20.6 SN65LV1224BRHBT VQFN RHB 32 250 210.0 185.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.