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     

SGLS128A − JULY 2002 − REVISED APRIL 2008

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Qualified for Automotive Applications

D ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

D Low-Voltage Differential 50-Ω Line Drivers

and Receivers

D Signaling Rates up to 500 Mbps

D Bus-Terminal ESD Exceeds 12 kV

D Operates From a Single 3.3 V Supply

D Low-Voltage Differential Signaling With

Typical Output Voltages of 340 mV With a

50-Ω Load

D Valid Output With as Little as 50-mV Input

Voltage Difference

D Propagation Delay Times

− Driver: 1.7 ns Typ

− Receiver: 3.7 ns Typ

D Power Dissipation at 200 MHz

− Driver: 50 mW Typical

− Receiver: 60 mW Typical

D LVTTL Input Levels Are 5 V Tolerant

D Driver Is High Impedance When Disabled or

With V

< 1.5 V

D Receiver Has Open-Circuit Fail Safe

description

The SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage

differential signaling (LVDS) to achieve signaling rates as high as 500 Mbps (per TIA/EIA-644 definition). These

circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts, except that the output

current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude

of 247 mV across a 50-Ω load simulating two transmission lines in parallel. This allows having data buses with

more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV

with up to 1 V of ground potential difference between a transmitter and receiver.

The intended application of these devices and signaling techniques is point-to-point and multipoint, baseband

data transmission over a controlled impedance media of approximately 100 Ω of characteristic impedance. The

transmission media may be printed-circuit board traces, backplanes, or cables.

GND

1DE

GND

2DE

SN65LVDM050QDQ1 (Marked as LVDM050Q)

(TOP VIEW)

SN65LVDM051QDQ1 (Marked as LVDM051Q)

(TOP VIEW)

1DE

2DE

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (25 pages)

PAGE 1
SGLS128A − JULY 2002 − REVISED APRIL 2008 D Qualified for Automotive Applications D ESD Protection Exceeds 2000 V Per D D D D D D D D D D D MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Low-Voltage Differential 50-Ω Line Drivers and Receivers Signaling Rates up to 500 Mbps Bus-Terminal ESD Exceeds 12 kV Operates From a Single 3.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 description (continued) The SN65LVDM050Q and SN65LVDM051Q are characterized for operation from −40°C to 125°C. Additionally, Q1 suffixed parts are qualified in accordance with AEC-Q100 stress test qualification for integrated circuits.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 equivalent input and output schematic diagrams VCC VCC VCC 300 kΩ 50 Ω 5Ω 10 kΩ D or RE Input Y or Z Output 50 Ω DE Input 7V 7V 7V 300 kΩ VCC VCC 300 kΩ 300 kΩ 5Ω A Input R Output B Input 7V 7V 7V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
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SGLS128A − JULY 2002 − REVISED APRIL 2008 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Voltage range (D, R, DE, RE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 driver electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VOD Differential output voltage magnitude ∆VOD Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-t
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SGLS128A − JULY 2002 − REVISED APRIL 2008 driver switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX 3 ns UNIT tPLH tPHL Propagation delay time, low-to-high-level output 1.7 Propagation delay time, high-to-low-level output 1.7 3 ns tr tf Differential output signal rise time 0.6 1.2 ns 0.6 1.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION driver IOY Driver Enable Y II A IOZ VOD V VOY Z VI OY )V OZ 2 VOC VOZ Figure 1. Driver Voltage and Current Definitions 3.75 kΩ Y Input DA 50 Ω VOD + _ Z 0 ≤ Vtest ≤ 2.4 V 3.75 kΩ 2V 1.4 V 0.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION driver (continued) 25 Ω, ±1% (2 Places) Driver Enable 3V Y Input 0V Z VOC VOC(PP) CL = 10 pF (2 Places) VOC(SS) VOC NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns .
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SGLS128A − JULY 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION receiver A V IA )V IB R VID 2 VIA B VIC VO VIB Figure 4. Receiver Voltage Definitions Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) RESULTING COMMONMODE INPUT VOLTAGE (V) VIC 1.2 VIA 1.225 VIB 1.175 VID 50 1.175 1.225 −50 1.2 2.375 2.325 50 2.35 2.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION driver Y Input DA 50 Ω VOD Z Figure 5. Timing Test Circuit 25 Ω, ±1% (2 Places) Y 0.8 V or 2 V Z DE 1.2 V CL = 10 pF (2 Places) VOY VOZ 2V 1.4 V 0.8 V DE VOY or VOZ tPZH ~1.4 V 1.25 V 1.2 V D at 2 V and input to DE 1.2 V 1.15 V ~1 V D at 0.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION receiver VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V −0.4 V tPHL VO tPLH VOH 2.4 V 1.4 V 0.4 V VOL tf tr NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 PARAMETER MEASUREMENT INFORMATION receiver (continued) 1.2 V B 500 Ω A Inputs RE CL 10 pF + − VO VTEST NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. 2.5 V VTEST A 1V 2V 1.
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SGLS128A − JULY 2002 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS COMMON-MODE INPUT VOLTAGE vs SUPPLY VOLTAGE 2.5 VIC − Common-Mode Input Voltage − V VCC > 3.15 V VCC = 3 V 2 1.5 1 0.5 MIN 0 0 0.1 0.2 0.4 0.3 0.5 0.6 |VID|− Differential Input Voltage − V Figure 9 DRIVER DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 3.5 VCC = 3.3 V TA = 25°C VCC = 3.
PAGE 14
SGLS128A − JULY 2002 − REVISED APRIL 2008 TYPICAL CHARACTERISTICS RECEIVER RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 5 4 VCC = 3.3 V TA = 25°C VOL − Low-Level Output Votlage − V VOH − High-Level Output Voltage − V VCC = 3.
PAGE 15
SGLS128A − JULY 2002 − REVISED APRIL 2008 RECEIVER RECEIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE−AIR TEMPERATURE 4.5 VCC = 3.3 V 4 VCC = 3 V 3.5 VCC = 3.6 V 3 2.
PAGE 16
SGLS128A − JULY 2002 − REVISED APRIL 2008 APPLICATION INFORMATION The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common-mode output and balanced interface for very low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds without the power and dual supply requirements.
PAGE 17
SGLS128A − JULY 2002 − REVISED APRIL 2008 APPLICATION INFORMATION fail safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDM050QDRQ1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDM051QDRG4Q1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDM051QDRQ1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDM050QDRQ1 SOIC D 16 2500 367.0 367.0 38.0 SN65LVDM051QDRG4Q1 SOIC D 16 2500 367.0 367.0 38.0 SN65LVDM051QDRQ1 SOIC D 16 2500 367.0 367.0 38.
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