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FEATURES

SN65LVDS048AD (Marked as LVDS048A)

SN65LVDS048APW (Marked as DL048A)

(TOP VIEW)

OUT1

OUT2

GND

OUT3

OUT4

functional diagram

IN1+

IN1–

IN2+

IN2–

IN3+

IN3–

IN4+

IN4–

OUT4

OUT3

OUT2

OUT1

IN1–

IN1+

IN2+

IN2–

IN3–

IN3+

IN4+

IN4–

DESCRIPTION

SN65LVDS048A

SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002

LVDS QUAD DIFFERENTIAL LINE RECEIVER

• >400 Mbps (200 MHz) Signaling Rates

• Flow-Through Pinout Simplifies PCB Layout

• 50 ps Channel-to-Channel Skew (Typ)

• 200 ps Differential Skew (Typ)

• Propagation Delay Times 2.7 ns (Typ)

• 3.3-V Power Supply Design

• High Impedance LVDS Inputs on Power Down

• Low-Power Dissipation (40 mW at 3.3 V Static)

• Accepts Small Swing (350 mV) Differential

Signal Levels

• Supports Open, Short, and Terminated Input

Fail-Safe

• Industrial Operating Temperature Range

(–40°C to 85°C)

• Conforms to TIA/EIA-644 LVDS Standard

• Available in SOIC and TSSOP Packages

• Pin-Compatible With DS90LV048A From

National

The SN65LVDS048A is a quad differential line receiver that implements the electrical characteristics of

low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V

differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and

allow operation with a 3.3-V supply rail. Any of the quad differential receivers will provide a valid logical output

state with a ±100-mV differential input voltage within the input common-mode voltage range. The input

common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes

The intended application of this device and signaling technique is for point-to-point baseband data transmission

over controlled impedance media of approximately 100 Ω . The transmission media may be printed-circuit board

traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation

characteristics of the media, the noise coupling to the environment, and other system characteristics.

The SN65LVDS048A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (13 pages)

PAGE 1
SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 LVDS QUAD DIFFERENTIAL LINE RECEIVER FEATURES • • • • • • • • • • • • • • >400 Mbps (200 MHz) Signaling Rates Flow-Through Pinout Simplifies PCB Layout 50 ps Channel-to-Channel Skew (Typ) 200 ps Differential Skew (Typ) Propagation Delay Times 2.7 ns (Typ) 3.3-V Power Supply Design High Impedance LVDS Inputs on Power Down Low-Power Dissipation (40 mW at 3.
PAGE 2
SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 DISSIPATION RATING TABLE (1) PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING D 950 mW 7.6 mW/°C 494 mW PW 774 mW 6.2 mW/°C 402 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS VCC MIN NOM MAX 3 3.3 3.
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SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT tPHL Differential propagation delay, high-to-low 1.9 2.7 3.7 ns tPLH Differential propagation delay, low-to-high 1.9 2.9 3.
PAGE 5
SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION RIN+ Generator RIN– R ROUT CL 50 Ω 50 Ω Receiver Enabled Figure 1. Receiver Propagation Delay and Transition Time Test Circuit RIN– 1.3 V OV Differential VID = 200 mV 1.2 V RIN+ 1.1 V tPLH ROUT tPHL 1.5 V 20% tr 80% 80% VOH 1.5 V 20% VOL tf Figure 2.
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SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION (continued) VCC RIN+ Generator RIN– EN 50 Ω S1 RL Device Under Test EN ROUT CL 1/4 65LVDS048A CL Includes Load and Test Jig Capacitance. S1 = VCC for tPZL and tPLZ Measurements. S1 = GND for tPZH and tPHZ Measurements. Figure 3. Receiver 3-State Delay Test Circuit 1.5 V EN When EN = GND or Open 1.
PAGE 7
SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS OUTPUT HIGH VOLTAGE vs POWER SUPPLY VOLTAGE OUTPUT LOW VOLTAGE vs POWER SUPPLY VOLTAGE 3.6 57 TA = 25°C VID = 200 mV VOL − Output Low Voltage − mV VOH − Output High Voltage − V TA = 25°C VID = 200 mV 3.4 3.2 3 2.8 3 3.3 56 55 54 53 52 3.6 3 VCC − Power Supply Voltage − V Figure 5. Figure 6.
PAGE 8
SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL PROPAGATION DELAY vs COMMON-MODE VOLTAGE 4 t PLH, t PHL − Differential Propagation Delay − ns t PLH, t PHL − Differential Propagation Delay − ns DIFFERENTIAL PROPAGATION DELAY vs DIFFERENTIAL INPUT VOLTAGE tPLH 3 tPHL 2 TA = 25°C f = 20 MHz VCM = 1.2 V CI = 15 pF VCC = 3.
PAGE 9
SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS048ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS048APWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS048ADR SOIC D 16 2500 346.0 346.0 33.0 SN65LVDS048APWR TSSOP PW 16 2000 346.0 346.0 29.
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