Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers, repeaters LVDS, PECL 2 GBit/s SOIC 8

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FEATURES DESCRIPTION

APPLICATIONS

FUNCTIONAL DIAGRAM

2 Gbps

- 1 PRBS

= 3.3 V

V

 = 200 mV

= 1.2 V

Horizontal Scale= 200 ps/div

Vert.Scale= 200 mV/div

EYE PATTERN

1 GHz

SN65LVDS100 and SN65LVDS101

110 Ω

SN65LVDT100 and SN65LVDT101

SN65LVDS100, SN65LVDT100

SN65LVDS101, SN65LVDT101

SLLS516C – AUGUST 2002 – REVISED JUNE 2004

DIFFERENTIAL TRANSLATOR/REPEATER

• Designed for Signaling Rates

(1)

≥ 2 Gbps

The SN65LVDS100, SN65LVDT100, SN65LVDS101,

and SN65LVDT101 are a high-speed differential re-

• Total Jitter < 65 ps

ceiver and driver connected as a repeater. The

• Low-Power Alternative for the MC100EP16

receiver accepts low-voltage differential signaling

• Low 100 ps (Max) Part-To-Part Skew

(LVDS), positive-emitter-coupled logic (PECL), or cur-

• 25 mV of Receiver Input Threshold Hysteresis rent-mode logic (CML) input signals at rates up to 2

Gbps and repeats it as either an LVDS or PECL

Over 0-V to 4-V Common-Mode Range

output signal. The signal path through the device is

• Inputs Electrically Compatible With LVPECL,

differential for low radiated emissions and minimal

CML, and LVDS Signal Levels

added jitter.

• 3.3-V Supply Operation

The outputs of the SN65LVDS100 and

• LVDT Integrates 110-Ω Terminating Resistor

SN65LVDT100 are LVDS levels as defined by

• Offered in SOIC and MSOP

TIA/EIA-644-A. The outputs of the SN65LVDS101

and SN65LVDT101 are compatible with 3.3-V PECL

levels. Both drive differential transmission lines with

nominally 100-Ω characteristic impedance.

• 622 MHz Central Office Clock Distribution

• High-Speed Network Routing

The SN65LVDT100 and SN65LVDT101 include a

110-Ω differential line termination resistor for less

• Wireless Basestations

board space, fewer components, and the shortest

• Low Jitter Clock Repeater

stub length possible. They do not include the V

• Serdes LVPECL Output to FPGA LVDS

voltage reference found in the SN65LVDS100 and

Input Translator

SN65LVDS101. V

provides a voltage reference of

typically 1.35 V below V

for use in receiving

single-ended input signals and is particularly useful

with single-ended 3.3-V PECL inputs. When not used,

should be unconnected or open.

(1) The signaling rate of a line is the number of voltage

All devices are characterized for operation from

transitions that are made per second expressed in the units

bps (bits per second). –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRO-

DUCTION DATA information current as of publication date. Prod-

ucts conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily

include testing of all parameters.

Summary of content (26 pages)

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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 DIFFERENTIAL TRANSLATOR/REPEATER FEATURES • • • • • • • • • DESCRIPTION Designed for Signaling Rates ≥ 2 Gbps Total Jitter < 65 ps Low-Power Alternative for the MC100EP16 Low 100 ps (Max) Part-To-Part Skew 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range Inputs Electrically Compatible With LVPECL, CML, and LVDS Signal Levels 3.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 RECOMMENDED OPERATING CONDITIONS MIN NOM Supply voltage, VCC 3 Magnitude of differential input voltage |VID| 3.6 'LVDS100 or 'LVDS101 0.1 1 'LVDT100 or 'LVDT101 0.1 0.8 Input voltage (any combination of common-mode or input signals), VI VBB output current, IO(VBB) Operating free-air temperature, TA (1) MAX UNIT 3.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION IIA VID VIC VIA+VIB Y B Z IO VBB VOD VIA VO(Y) VIB 2 A + VBB - VOC VO(Z) IIB Figure 1. Voltage and Current Definitions Table 1. Receiver Input Voltage Threshold Test APPLIED VOLTAGES (1) RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE OUTPUT (1) VIA VIB VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 VOY + VOD VOZ 50 Ω 50 Ω + - VCC - 2V Figure 4. Typical Termination for LVPECL Output Driver (65LVDx101) A Y VOD 1 pF VID VIA B 100 Ω Z VIA 1.4 V VIB 1V VID 0.4 V 0V -0.4 V VIB VOD OR 50 Ω tPHL tPLH 100% 0V 80% 50 Ω VOD + - 20% VCC - 2V tf 0% tr NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 0.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 Power Supply 1 + 3.3V - + Power Supply 2 1.22V J3 DUT GND J2 J1 VCC EVM GND J6 J4 100 J5 Agilent E4862B Pattern Generator (Note A) J7 50 DUT Matched Cables SMA to SMA Matched Cables SMA to SMA Tektronix TDS6604 Oscilloscope (Note B) EVM A. Source jitter is subtracted from the measured values. B. TDS JIT3 jitter analysis software installed 50 Figure 7.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY SUPPLY CURRENT vs FREE-AIR TEMPERATURE 55 DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY 60 700 V OD - Differential Output Voltage - mV LVDS101= Loaded 50 VCC = 3.3 V TA = 25°C VIC = 1.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) SN65LVDS101 PEAK-TO-PEAK JITTER vs FREQUENCY SN65LVDS101 PEAK-TO-PEAK JITTER vs DATA RATE 60 VCC = 3.3 V TA = 25°C VIC = 400 mV Input = Clock 50 Peak-To-Peak Jitter - ps 20 15 VID = 0.8 V 10 VID = 0.3 V 40 VID = 0.5 V VID = 0.8 V 30 20 10 5 0 200 400 600 800 0 300 1000 15 VID = 0.8 V VID = 0.5 V 10 VID = 0.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) SN65LVDS100 PEAK-TO-PEAK JITTER vs FREE-AIR TEMPERATURE 60 VID = 0.5 V 30 20 30 1800 60 LVDS101 50 VCC = 3.3 V, VIC = 1.2 V, |V ID| = 200 mV, TA = 25°C, Input = Clock 150 0 -40 40 30 100 20 50 10 Added Random Jitter 0 -20 0 20 40 60 80 TA - Free-Air Temperature - °C 0 100 500 1000 1500 2000 Figure 27. Figure 28.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) SN65LVDS100 622 Mbps, 223– 1 PRBS Horizontal Scale= 200 ps/div LVPECL-to-LVDS Horizontal Scale= 100 ps/div LVPECL-to-LVDS Figure 32. Figure 33. SN65LVDS101 622 Mbps, 223– 1 PRBS SN65LVDS101 2 Gbps, 223– 1 PRBS Horizontal Scale= 200 ps/div LVDS-to-LVPECL Figure 34. 12 SN65LVDS100 2 Gbps, 223– 1 PRBS Horizontal Scale= 100 ps/div LVDS-to-LVPECL Figure 35.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) 20 3.6 V, 85°C 3 V, 85°C Input Voltage Threshold - mV 15 3.6 V, -40°C 10 VIT+ 5 3 V, -40°C 0 |VOD| = 250 mV, RL = 100 Ω, Nominal Process 3 V, -40°C -5 -10 VIT- 3.6 V, -40°C -15 3.6 V, 85°C -20 0 1 3 V, 85°C 2 3 4 Common-Mode Input Voltage - V 5 NOTE: VIT is a steady-state parameter.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 APPLICATION INFORMATION The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 inputs will detect a 100-mV difference between any two signals between 0 V and 4 V, This range will allow receipt of many different single-ended and differential signals. Following are some of the more common connections. VCC SN65LVDS100 ECL 100 VEE 50 50 VCC-2 V Figure 37.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) 3.3 V ECL SN65LVDS100 Z0 = 50 100 50 VEE LVDS VBB 0.01 F 22 k Figure 41. Single-Ended 3.3-V PECL-to-LVDS Translation VDD VDD/600 A* 1 V < VDD < 4 V CMOS SN65LVDS100 100 0.01 F LVDS VDD/600 A* * closest standard value Figure 42. Single-Ended CMOS-to-LVDS Translation VDD 1 V < VDD < 4 V VDD/600 A* CMOS SN65LVDS101 3.3 v PECL 50 0.
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SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 www.ti.com SLLS516C – AUGUST 2002 – REVISED JUNE 2004 APPLICATION INFORMATION (continued) FAILSAFE CONSIDERATIONS Failsafe, in regard to a line receiver, usually means that the output goes to a defined logical state with no input signal. To keep added jitter to an absolute minimum, the SN65LVDS100 does not include this feature.
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www.ti.com SN65LVDS100, SN65LVDT100 SN65LVDS101, SN65LVDT101 SLLS516C – AUGUST 2002 – REVISED JUNE 2004 Figure 46.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 19-Oct-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS100DGKR Package Package Pins Type Drawing VSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65LVDS100DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65LVDS101DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS100DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 SN65LVDS100DR SOIC D 8 2500 367.0 367.0 35.0 SN65LVDS101DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 SN65LVDS101DR SOIC D 8 2500 367.0 367.0 35.0 SN65LVDT100DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 SN65LVDT100DR SOIC D 8 2500 367.0 367.0 35.
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