Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers LVDS 400 Mbit/s TSSOP 16

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FEATURES

DESCRIPTION

EN1

EN2

’LVDS104

EN4

logic diagram (positive logic)

EN3

EN1

EN2

’LVDS105

EN4

EN3

EN1

EN2

EN3

GND

EN4

SN65LVDS104

D OR PW PACKAGE

(Marked as LVDS104)

(TOP VIEW)

EN1

EN2

EN3

GND

EN4

SN65LVDS105

D OR PW PACKAGE

(Marked as LVDS105)

(TOP VIEW)

SN65LVDS104

SN65LVDS105

SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

• Receiver and Drivers Meet or Exceed the

Requirements of ANSI EIA/TIA-644 Standard

– SN65LVDS105 Receives Low-Voltage TTL

(LVTTL) Levels

– SN65LVDS104 Receives Differential Input

Levels, ± 100 mV

• Typical Data Signaling Rates to 400 Mbps or

Clock Frequencies to 400 MHz

• Operates From a Single 3.3-V Supply

• Low-Voltage Differential Signaling With

Typical Output Voltage of 350 mV and a 100- Ω

Load

• Propagation Delay Time

– SN65LVDS105 – 2.2 ns (Typ)

– SN65LVDS104 – 3.1 ns (Typ)

• LVTTL Levels Are 5-V Tolerant

• Electrically Compatible With LVDS, PECL,

LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,

SSTL, or HSTL Outputs With External

Networks

• Driver Outputs Are High Impedance When

Disabled or With V

<1.5 V

• Bus-Pin ESD Protection Exceeds 16 kV

• SOIC and TSSOP Packaging

The SN65LVDS104 and SN65LVDS105 are a differ-

ential line receiver and a LVTTL input (respectively)

connected to four differential line drivers that im-

plement the electrical characteristics of low-voltage

differential signaling (LVDS). LVDS, as specified in

EIA/TIA-644 is a data signaling technique that offers

low-power, low-noise coupling, and switching speeds

to transmit data at relatively long distances. (Note:

The ultimate rate and distance of data transfer is

dependent upon the attenuation characteristics of the

media, the noise coupling to the environment, and

other system characteristics.)

The intended application of this device and signaling technique is for point-to-point baseband data transmission

over controlled impedance media of approximately 100 Ω . The transmission media may be printed-circuit board

traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse

skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.

This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS FEATURES • • • • • • • • • • Receiver and Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard – SN65LVDS105 Receives Low-Voltage TTL (LVTTL) Levels – SN65LVDS104 Receives Differential Input Levels, ±100 mV Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz Operates From a Single 3.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40°C to 85°C. The SN65LVDS104 and SN65LVDS105 are members of a family of LVDS repeaters.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT (2) Supply voltage range, VCC –0.5 to 4 V Enables, A ('LVDS105) Voltage range –0.5 to 6 V A, B, Y or Z Electrostatic discharge (3) –0.
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SN65LVDS104 SN65LVDS105 www.ti.
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SN65LVDS104 SN65LVDS105 www.ti.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 PARAMETER MEASUREMENT INFORMATION II IOY A Y IIB VID VOD IOZ V VOY Z VIA B OY V OZ 2 VOC VIB VOZ Figure 1. 'LVDS104 Voltage and Current Definitions Table 1. SN65LVDS104 Minimum and Maximum Input Threshold Test Voltages RESULTING DIFFERENTIAL INPUT VOLTAGE APPLIED VOLTAGES RESULTING COMMON-MODE INPUT VOLTAGE VIA VIB VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 49.9 Ω ± 1% (2 Places) Y Input (see Note A) VI 1.4 V VI 1V Z VOC(PP) CL = 10 pF (2 Places) (see Note B) VOC VOC(SS) VO A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns. B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 49.9 Ω ± 1% (2 Places) Y 1 V or 1.4 V Input (see Note A) Z 1.2 V 1.2 V EN CL = 10 pF (2 Places) (see Note B) VOY VOZ 3V 1.5 V 0V EN tPZH tPHZ ≅ 1.4 V 1.25 V 1.2 V VOY or VOZ tPZL tPLZ 1.2 V 1.15 V ≅1V VOZ or VOY A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns. B.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 49.9 Ω ± 1% (2 Places) 3V Y Input (see Note A) A 0V Z VOC(PP) VOC CL = 10 pF (2 Places) (see Note B) VOC(SS) VO A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns. B. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 Y 49.9 Ω ± 1% (2 Places) 0.8 V or 2 V Z Input (see Note A) 1.2 V EN CL = 10 pF (2 Places) (see Note B) VOY VOZ 3V 1.5 V 0V EN tPZH tPHZ VOY or VOZ ≅ 1.4 V 1.25 V 1.2 V tPZL tPLZ VOZ or VOY 1.2 V 1.15 V ≅1V A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns. B.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 TYPICAL CHARACTERISTIC SN65LVDS104 SUPPLY CURRENT vs FREQUENCY SN65LVDS105 SUPPLY CURRENT vs FREQUENCY 60 50 45 I CC − Supply Current − mA I CC − Supply Current − mA 55 50 VCC = 3.6 V 45 VCC = 3 V 40 35 VCC = 3.3 V 40 VCC = 3.6 V 35 VCC = 3 V 30 VCC = 3.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 TYPICAL CHARACTERISTIC (continued) SN65LVDS104 HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 3.6 t PHL − High-To-Low Propagation Delay Time − ns t PLH − Low-To-High Propagation Delay Time − ns SN65LVDS104 LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 3.5 3.4 VCC = 3.3 V 3.3 3.2 VCC = 3 V 3.1 VCC = 3.6 V 3.0 2.9 2.8 −50 −25 0 25 50 75 100 3.6 3.5 3.4 3.3 VCC = 3 V 3.2 VCC = 3.3 V 3.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 TYPICAL CHARACTERISTIC (continued) SN65LVDS104 P-P EYE-PATTERN JITTER vs PRBS SIGNALING RATE 800 TA = 25 C 700 Peak-to-Peak Jitter − ps VCC = 3.6 V 600 500 VCC = 3 V 400 300 200 100 0 0 100 200 300 400 500 600 Signaling Rate − Mbps NOTES: Input: 215 PRBS with peak-to-peak jitter <115 ps at 100 Mbps. Test board adds about 70 ps p-p jitter.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 TYPICAL CHARACTERISTIC (continued) SN65LVDS105 P-P EYE-PATTERN JITTER vs PRBS SIGNALING RATE 600 TA = 25 C VCC = 3.6 V Peak-to-Peak Jitter − ps 500 VCC = 3 V 400 300 200 100 0 0 100 200 300 400 500 600 Signaling Rate − Mbps NOTES: Input: 215 PRBS with peak-to-peak Jitter < 147 ps at 100 Mbps, Test board adds about 43 ps p-p jitter.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 APPLICATION INFORMATION INPUT LEVEL TRANSLATION An LVDS receiver can be used to receive various other types of logic signals. Figure 23 through Figure 32 show the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL. VDD 25 Ω 50 Ω A 1/2 VDD 50 Ω B 0.1 µF LVDS Receiver Figure 23. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL) VDD 50 Ω A 50 Ω B 1.35 V < VTT < 1.65 V 0.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 APPLICATION INFORMATION (continued) Z0 Z0 A B 1.47 V < VTT < 1.62 V 0.1 µF LVDS Receiver Figure 26. Backplane Transceiver Logic (BTL) 3.3 V 3.3 V 50 Ω 120 Ω 120 Ω 33 Ω ECL A 50 Ω 33 Ω B 51 Ω 51 Ω LVDS Receiver Figure 27.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 APPLICATION INFORMATION (continued) 5V 5V 82 Ω 50 Ω 82 Ω 100 Ω ECL A 50 Ω 100 Ω B 33 Ω 33 Ω LVDS Receiver Figure 28. Positive Emitter-Coupled Logic (PECL) 3.3 V 3.3 V 7.5 kΩ A B 7.5 kΩ 0.1 µF LVDS Receiver Figure 29. 3.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 APPLICATION INFORMATION (continued) 5V 5V 10 kΩ 560 Ω A B 560 Ω 3.32 kΩ 0.1 µF LVDS Receiver Figure 30. 5-V CMOS 5V 5V 10 kΩ 470 Ω A B 3.3 V 4.02 kΩ 0.1 µF LVDS Receiver Figure 31. 5-V TTL 3.3 V 3.3 V 4.02 kΩ 560 Ω A B 3.01 kΩ Figure 32. LVTTL 18 0.
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SN65LVDS104 SN65LVDS105 www.ti.com SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005 APPLICATION INFORMATION (continued) FAIL SAFE A common problem with differential signaling applications is how the system responds when no differential voltage is present on the signal pair.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.3 2.1 8.0 16.0 Q1 SN65LVDS104DR SOIC D 16 2500 330.0 16.4 6.5 SN65LVDS104PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDS105DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS104DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDS104PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDS105DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDS105PWR TSSOP PW 16 2000 367.0 367.0 35.
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