Datasheet

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FEATURES

GND

ENM

ENA

ENB

ENC

END

ENE

ENF

ENG

ENH

GND

DBT PACKAGE

(TOP VIEW)

NC – No internal connection

DESCRIPTION

SN65LVDS108

SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005

8-PORT LVDS REPEATER

• One Line Receiver and Eight Line Drivers

Configured as an 8-Port LVDS Repeater

• Line Receiver and Line Drivers Meet or

Exceed the Requirements of ANSI EIA/TIA-644

Standard

• Typical Data Signaling Rates to 400 Mbps or

Clock Frequencies to 400 MHz

• Enabling Logic Allows Individual Control of

Each Driver Output, Plus All Outputs

• Low-Voltage Differential Signaling With

Typical Output Voltage of 350 mV and a 100- Ω

Load

• Electrically Compatible With LVDS, PECL,

LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,

SSTL, or HSTL Outputs With External

Termination Networks

• Propagation Delay Times < 4.7 ns

• Output Skew Less Than 300 ps and

Part-to-Part Skew Less Than 1.5 ns

• Total Power Dissipation at 200 MHz Typically

Less Than 330 mW With 8 Channels Enabled

• Driver Outputs or Receiver Input Equals High

Impedance When Disabled or With V

< 1.5 V

• Bus-Pin ESD Protection Exceeds 12 kV

• Packaged in Thin Shrink Small-Outline

Package With 20-Mil Terminal Pitch

The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers.

Individual output enables are provided for each output and an additional enable is provided for all outputs.

The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling

(LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise

emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer

is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other

system characteristics.)

The intended application of this device, and the LVDS signaling technique, is for point-to-point or

point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of

approximately 100 Ω . The transmission media may be printed-circuit board traces, backplanes, or cables. The

large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced

signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is

particularly advantageous for implementing system clock or data distribution trees.

The SN65LVDS108 is characterized for operation from –40 ° C to 85 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

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SN65LVDS108 www.ti.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65LVDS108 www.ti.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3.3 3.6 VCC Supply voltage 3 VIH High-level input voltage 2 VIL Low-level input voltage VI or VIC Voltage at any bus terminal (separately or common-mode) TA Operating free-air temperature UNIT V V 0.8 V 0 VCC– 0.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX tPLH Propagation delay time, low-to-high-level output 1.6 2.8 4.5 tPHL Propagation delay time, high-to-low-level output 1.6 2.8 4.5 tr Differential output signal rise time 0.3 0.8 1.2 tf Differential output signal fall time 0.3 0.8 1.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 3.75 kΩ Y 100 Ω 3.75 kΩ VOD Input Z ± 0 V ≤ VTEST ≤ 2.4 V Figure 2. VOD Test Circuit 49.9 Ω ± 1% (2 Places) Y Input Input VI 1.4 V VI 1V Z 50 pF VOC(PP) VOC(SS) VOC VO A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 Y 1 V or 1.4 V 49.9 Ω ± 1% (2 Places) Z 1.4 V or 1 V 1.2 V CL = 10 pF ENM (2 Places) ENx Inputs VOY 2V 1.4 V 0.8 V Input tPZH tPHZ VOY or VOZ 100%, ≅ 1.4 V 50% 0%, 1.2 V tPZL VOZ or VOY A. VOZ tPLZ 100%, 1.2 V 50% 0%, ≅ 1 V All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns .
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SWITCHING FREQUENCY LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE t PLH − Low-To-High Propagation Delay Time − ns 140 I CC − Supply Current − mA 120 VCC = 3.6 V 100 VCC = 3 V 80 VCC = 3.3 V 60 40 20 All Outputs Loaded and Enabled 0 0 50 100 150 200 250 300 350 3.8 3.7 3.6 3.5 VCC = 3.3 V 3.4 VCC = 3 V VCC = 3.6 V 3.3 3.2 3.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS (continued) P-P EYE-PATTERN JITTER vs PRBS SIGNALING RATE 700 TA = 25 C 600 Peak-to-Peak Jitter − ps VCC = 3.6 V 500 VCC = 3 V 400 300 200 100 00 100 200 300 400 500 Signaling Rate − Mbps NOTES: Input: 215 PRBS with peak-to-peak jitter < 100 ps at 100 Mbps, all outputs enabled and loaded with differential 100-Ω loads, worst-case output, supply decoupled with 0.1-µF and 0.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION FAIL SAFE A common problem with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION (continued) The enable inputs provided for each output may be used to turn on or off any of the paths. This function is required to prevent radiation of signals from the unterminated signal lines on open connectors when boards or devices are being swapped in the end equipment. The individual channel enables are also required if redundant paths are being utilized for reliability reasons.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION (continued) VDD 50 Ω A 50 Ω B 1.35 V < VTT < 1.65 V 0.1 µF LVDS Receiver Figure 15. Center-Tap Termination (CTT) 1.14 V < VTT < 1.26 V VDD 50 Ω 1 kΩ 50 Ω A B 2 kΩ 0.1 µF LVDS Receiver Figure 16. Gunning Transceiver Logic (GTL) Z0 Z0 A B 1.47 V < VTT < 1.62 V 0.1 µF Figure 17.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION (continued) 3.3 V 3.3 V 50 Ω 120 Ω 120 Ω 33 Ω ECL A 50 Ω 33 Ω B 51 Ω 51 Ω LVDS Receiver Figure 18. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 5V 5V 50 Ω 82 Ω 82 Ω 100 Ω ECL A 50 Ω 100 Ω 33 Ω B 33 Ω LVDS Receiver Figure 19.
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SN65LVDS108 www.ti.com SLLS399E – NOVEMBER 1999 – REVISED FEBRUARY 2005 APPLICATION INFORMATION (continued) 3.3 V 3.3 V 7.5 kΩ A B 7.5 kΩ 0.1 µF LVDS Receiver Figure 20. 3.3-V CMOS 5V 5V 10 kΩ 560 Ω A B 560 Ω 3.32 kΩ 0.1 µF LVDS Receiver Figure 21. 5-V CMOS 5V 5V 10 kΩ 470 Ω A B 3.3 V 4.02 kΩ Figure 22. TTL 14 0.
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PACKAGE OPTION ADDENDUM 31 – January – 2011 Addendum Page 1
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PACKAGE OPTION ADDENDUM 31 – January – 2011 TAPE AND REEL INFORMATION Addendum Page 2
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PACKAGE OPTION ADDENDUM 31 – January – 2011 PACKAGE INFORMATION Orderable Device Status (1) Pkg Type Pkg Drawing Pins Pkg Qty SN65LVDS108DBT ACTIVE TSSOP DBT 38 50 SN65LVDS108DBTG4 ACTIVE TSSOP DBT 38 50 SN65LVDS108DBTR ACTIVE TSSOP DBT 38 2000 SN65LVDS108DBTRG4 ACTIVE TSSOP DBT 38 2000 Eco Plan (2) Green (RoHS & no Sb/ Br) Green (RoHS & no Sb/ Br) Green (RoHS & no Sb/ Br) Green (RoHS & no Sb/ Br) Lead/ Ball Finish MSL Peak Temp (3) CU NIPDAU Level-2-260C-UNLIM CU NIPDAU
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS108DBTR Package Package Pins Type Drawing TSSOP DBT 38 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS108DBTR TSSOP DBT 38 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.