Datasheet

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FEATURES DESCRIPTION

APPLICATIONS

FUNCTIONAL DIAGRAM

1.5 Gbps

− 1 PRBS

= 3.3 V

V

 = 200 mV, V

= 1.2 V

Horizontal Scale= 200 ps/div

Vertical Scale=200 mV/div

EYE PATTERNS OF OUTPUTS

OPERATING SIMULTANEOUSLY

MUX

1DE

2DE

Integrated Termination on SN65LVDT122 Only

OUTPUT 1

OUTPUT 2

110 Ω

SN65LVDS122

SN65LVDT122

SLLS525B – MAY 2002 – REVISED JUNE 2004

1.5-Gbps 2 × 2 LVDS CROSSPOINT SWITCH

• Designed for Signaling Rates

(1)

Up To

The SN65LVDS122 and SN65LVDT122 are

1.5 Gbps

crosspoint switches that use low voltage differential

signaling (LVDS) to achieve signaling rates as high

• Total Jitter < 65 ps

as 1.5 Gbps. They are pin-compatible speed up-

• Pin-Compatible With SN65LVDS22 and

grades to the SN65LVDS22 and SN65LVDM22. The

SN65LVDM22

internal signal paths maintain differential signaling for

• 25 mV of Receiver Input Threshold Hysteresis

high speeds and low signal skews. These devices

Over 0-V to 4-V Common-Mode Range

have a 0-V to 4-V common-mode input range that

accepts LVDS, LVPECL, or CML inputs. Two logic

• Inputs Electrically Compatible With CML,

pins (S0 and S1) set the internal configuration be-

LVPECL and LVDS Signal Levels

tween the differential inputs and outputs. This allows

• Propagation Delay Times, 900 ps Maximum

the flexibility to perform the following configurations:

• LVDT Integrates 110-Ω Terminating Resistor

2 x 2 crosspoint switch, 2:1 input multiplexer, 1:2

splitter or dual repeater/translator within a single

• Offered in SOIC and TSSOP

device. Additionally, SN65LVDT122 incorporates a

110-Ω termination resistor for those applications

where board space is a premium. Although these

• 10-G (OC-192) Optical Modules

devices are designed for 1.5 Gbps, some applications

• 622-MHz Central Office Clock Distribution

at a 2-Gbps data rate can be supported depending on

loading and signal quality.

• Wireless Basestations

• Low Jitter Clock Repeater/Multiplexer

The intended application of this device is ideal for

loopback switching for diagnostic routines, fanout

• Protection Switching for Serial Backplanes

buffering of clock/data distribution provide protection

in fault-tolerant systems, clock multiplexing in optical

modules, and for overall signal boosting over

extended distances.

(1) The signlaing rate of a line is the number of voltage

The SN65LVDS122 and SN65LVDT122 are

transitions that are made per second expressed in the units

characterized for operation from –40°C to 85°C.

bps (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 1.5-Gbps 2 × 2 LVDS CROSSPOINT SWITCH FEATURES • DESCRIPTION Designed for Signaling Rates Up To 1.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65LVDS122 SN65LVDT122 www.ti.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 TIMING CHARACTERISTICS PARAMETER tSET Input to select setup time tHOLD Input to select hold time tSWITCH Select to switch output TEST CONDITIONS MIN NOM MAX UNIT 0 ns 0.5 ns 1 2 2.
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SN65LVDS122 SN65LVDT122 www.ti.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION IIA VID VIA (VIA+VIB)/2 A Y B Z VOD VOY VIC VIB IIB (VOY+VOZ)/2 VOZ Figure 1. Voltage and Current Definitions 3.74 kΩ Y VOD 100 Ω Z 3.74 kΩ + _ 0 V ≤ Vtest ≤ 2.4 V Figure 2. Differential Output Voltage (VOD) Test Circuit A Y B Z A ≈ 1.4 V B ≈1V 49.9 Ω ±1% VID VOC(PP) 49.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION (continued) 49.9 Ω ±1% Y 1 V or 1.4 V 1.2 V DE A 1 pF B 49.9 Ω ±1% Z 3V 1.5 V 0V DE ≅ 1.4 V 1.25 V 1.2 V VOY or VOZ 1.2 V tPZH tPHZ 1.2 V 1.15 V ≅1V VOZ or VOY tPZL tPLZ NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION (continued) t(SET) and t(HOLD) times specify that data must be in a stable state before and after multiplex control switches. Table 1. Receiver Input Voltage Threshold Test APPLIED VOLTAGES (1) 8 RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE OUTPUT (1) VIA VIB VID VIC 1.25 V 1.15 V 100 mV 1.2 V 1.15 V 1.25 V –100 mV 1.2 V L 4.0 V 3.9 V 100 mV 3.
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SN65LVDS122 SN65LVDT122 www.ti.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS DIFFERENTIAL OUTPUT VOLTAGE vs FREQUENCY DIFFERENTIAL PROPAGATION DELAY vs COMMON-MODE INPUT VOLTAGE 1000 300 250 200 150 VCC = 3.3 V TA = 25°C VIC = 1.2 V VID = 200 mV Input = Clock 100 50 800 VCC = 3.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) PEAK-TO-PEAK JITTER vs TEMPERATURE PEAK-TO-PEAK JITTER vs DATA RATE 50 VCC = 3.3 V TA = 25°C VIC = 1.2 V |V ID |= 200 m V Input = PRBS 223 −1 90 Peak-To-Peak Jitter − ps Peak-To-Peak Jitter - ps 40 100 VCC = 3.3 V TA = 25°C VIC = 1.2 V VID = 200 mV Input = 1.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 TYPICAL CHARACTERISTICS (continued) LVDS122 622 Mbps, 223– 1 PRBS LVDS122 1.5 Gbps, 223– 1 PRBS VCC = 3.3 V TA = 25°C VID = 200 mV VCC = 3.3 V TA = 25°C VID = 200 mV Horizontal Scale= 200 ps/div LVDS-to-LVDS Horizontal Scale= 100 ps/div LVDS-to-LVDS Figure 20. Power Supply 1 Figure 21. + 3.3 V − Power Supply 2 + 1.
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SN65LVDS122 SN65LVDT122 www.ti.com SLLS525B – MAY 2002 – REVISED JUNE 2004 APPLICATION INFORMATION TYPICAL APPLICATION CIRCUITS (ECL, PECL, LVDS, etc.) 50 Ω 3.3 V or 5 V 3.3 V SN65LVDS122 A ECL B 50 Ω 50 Ω 50 Ω VTT = VCC −2 V VTT Figure 23. Low-Voltage Positive Emitter-Coupled Logic (LVPECL) 3.3 V 50 Ω 50 Ω 3.3 V 3.3 V SN65LVDS122 A CML B 50 Ω 50 Ω 3.3 V Figure 24. Current-Mode Logic (CML) 3.3 V SN65LVDS122 3.3 V 50 Ω A ECL B 50 Ω 1.1 kΩ VTT 1.5 kΩ VTT = VCC −2 V VCC Figure 25.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS122DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS122PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDT122PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS122DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDS122PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDT122PWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.