Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - buffer amplifiers LVDS 250 Mbit/s TSSOP 16

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FEATURES

DESCRIPTION

1DE

GND

2DE

GND

logic diagram (positive logic)

1DE

2DE

1Y/1Z

1A/1B

2A/2B

1A/1B

2A/2B

2Y/2Z

1A/1B

2A/2B

1A/1B

Splitter

Router

INPUT OUTPUT

FUNCTION

MUX TRUTH TABLE

SN65LVDS22D and SN65LVDS22PW (Marked as LVDS22)

SN65LVDM22D and SN65LVDM22PW (Marked as LVDM22)

(TOP VIEW)

SN65LVDS22

SN65LVDM22

SLLS315C – DECEMBER 1998 – REVISED JUNE 2002

DUAL MULTIPLEXED LVDS REPEATERS

• Meets or Exceeds the Requirements of ANSI

TIA/EIA-644-1995 Standard

• Designed for Clock Rates up to 200 MHz

(400 Mbps)

• Designed for Data Rates up to 250 Mbps

• Pin Compatible With SN65LVDS122 and

SN65LVDT122, 1.5 Gbps 2x2 Crosspoint

Switch From TI

• ESD Protection Exceeds 12 kV on Bus Pins

• Operates From a Single 3.3-V Supply

• Low-Voltage Differential Signaling With

Output Voltages of 350 mV Into:

– 100- Ω Load (SN65LVDS22)

– 50- Ω Load (SN65LVDM22)

• Propagation Delay Time; 4 ns Typ

• Power Dissipation at 400 Mbps of 150 mW

• Bus Pins Are High Impedance When Disabled

or With V

Less Than 1.5 V

• LVTTL Levels Are 5 V Tolerant

• Open-Circuit Fail Safe Receiver

The SN65LVDS22 and SN65LVDM22 are differential

line drivers and receivers that use low-voltage

differential signaling (LVDS) to achieve signaling

rates as high as 400 Mbps. The receiver outputs can

be switched to either or both drivers through the

multiplexer control signals S0 and S1. This allows the

flexibility to perform splitter or signal routing functions

with a single device.

The TIA/EIA-644 standard compliant electrical

interface provides a minimum differential output

voltage magnitude of 247 mV into a 100- Ω load and

receipt of 100 mV signals with up to 1 V of ground

potential difference between a transmitter and

receiver. The SN65LVDM22 doubles the output drive

current to achieve LVDS levels with a 50- Ω load.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 DUAL MULTIPLEXED LVDS REPEATERS FEATURES • • • • • • • • • • • • Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard Designed for Clock Rates up to 200 MHz (400 Mbps) Designed for Data Rates up to 250 Mbps Pin Compatible With SN65LVDS122 and SN65LVDT122, 1.5 Gbps 2x2 Crosspoint Switch From TI ESD Protection Exceeds 12 kV on Bus Pins Operates From a Single 3.
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SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables.
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SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 DISSIPATION RATING TABLE (1) PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING D 1110 mW 8.9 mW/°C 577 mW PW 839 mW 6.7 mW/°C 437 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
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SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input voltage threshold VIT– Negative-going differential input voltage threshold II Input current (A or B inputs) II(OFF Power-off input current (A or B inputs) MIN TYP MAX UNIT 100 mV 100 VI = 0 V mV 2 VI = 2.4 V 20 1.
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SN65LVDS22 SN65LVDM22 www.ti.
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SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION (continued) DE A Y B Z Pulse Generator RL (see Note B) (2 Places) VI(B) 1.4 V VI(A) 1V VOC(PP) Input (see Note A) VOC CL = 10 pF (2 Places) (see Note C) (see Note D) VOC(SS) VCC A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ±0.2 ns. B. RL = 100 Ω or 50 Ω ±1% C.
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SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION (continued) DE 1 V or 1.4 V R 1.2 V RL/2 (see Note A) A 1.2 V D B RL/2 (see Note A) 2V DE 1.4 V 0.8 V tPZH tPHZ ≈1.4 V VOY or VOZ 1.25 V 1.2 V tPZL tPLZ 1.2 V 1.15 V VOY or VOZ ≈1 V A. RL = 100 Ω or 50 Ω ±1% B. All input pulses are supplied by a generator having the following characteristics: pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ±10 ns. Figure 5.
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SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION (continued) 1A/B 2A/B tsu th S0/1 Outputs Out 1 or 2 Out 1 or 2 tsu DE NOTE: tsu and th times specify that data must be in a stable state before and after MUX control switches. Figure 6.
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SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 TYPICAL CHARACTERISTICS SN65LVDS22 HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25°C V OL − Low-Level Output Voltage − V V OH − High-Level Ouptut Voltage − V 3.5 SN65LVDS22 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3 2.5 2 1.5 1 VCC = 3.3 V TA = 25°C 3 2 1 .5 0 0 −4 −3 −2 −1 0 0 IOH − High-Level Output Current − mA Figure 7. Figure 8.
PAGE 11
SN65LVDS22 SN65LVDM22 www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 APPLICATION INFORMATION FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2009 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS22DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS22PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS22DR SOIC D 16 2500 346.0 346.0 33.0 SN65LVDS22PWR TSSOP PW 16 2000 346.0 346.0 29.
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