Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - serialisers LVDS VQFN 24

FPC

LVDS315

Application

processor

with

integrated

MIPICSI-1

receiver

RGBIF

Camera

SN65LVDS315

www.ti.com

SLLS881F –DECEMBER 2007–REVISED SEPTEMBER 2012

CAMERA PARALLEL RGB TO MIPI CSI-1 SERIAL CONVERTER

Check for Samples: SN65LVDS315

The serialized data is presented on the differential

FEATURES

serial data output DOUT with a differential clock

• MIPI CSI-1 and SMIA CCP Support

signal on output CLK. The frequency of CLK is 8× the

• Connects Directly to OMAP CSI Interface

DCLK input pixel clock rate.

• 4×4 mm QFN Package

Flexible printed circuit (FPC) cabling typically

• ESD Rating >3 kV (HBM) Camera Input Ports

interconnects the SN65LVDS315 with the CSI-1

compliant receiver. Compared to parallel signalling,

and >2 kV (HBM) All Other Ports

the SN65LVDS315 outputs significantly reduce the

• Pixel Clock Range 3.5–27 MHz

EMI of the interconnect.

• Three Operating Modes to Conserve Power

A certain differential termination circuit must be

– Active Mode VGA Camera 30 fps: 7 mA

implemented at the CSI-1 receiver, involving two

– Typical Shutdown and Standby: 0.5 μA

50 Ω resistors and one 0.1 µF capacitor. For more

details, see the APPLICATION INFORMATION

• EMI

section.

APPLICATIONS

The SN65LVDS315 supports three power modes

(shutdown, standby and active) to conserve power.

• Camera to Host Controller (e.g. OMAP2420,

The TXEN input may be used to put the

OMAP2430, OMAP3430)

SN65LVDS315 in a shutdown mode. The

• Mobile Phones and Smart Phones

SN65LVDS315 enters an active standby mode if the

input clock, DCLK, stops. This minimizes power

DESCRIPTION

consumption without the need for controlling an

external terminal.

The SN65LVDS315 is a camera serializer that

converts 8-bit parallel camera data into MIPI-CSI1 or

The SN65LVDS315 is characterized for operation

SMIA CCP compliant serial signals.

over ambient air temperatures of –40°C to 85°C. All

CMOS inputs offer failsafe operation to protect the

The device converts the parallel 8-bit data to two sub-

input from damage during power up and to avoid

low-voltage differential signaling (SubLVDS) serial

current flow into the device inputs during power up.

data and clock output. The parallel data is latched in

The core supply of the SN65LVDS315 is 1.8 V. To

with the pixel clock input DCLK on the falling clock

provide greater flexibility, the camera data inputs

edge. The control inputs VS and HS are used to

support a supply range from 1.8 V to 3.3 V.

determine line and frame synchronization.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 CAMERA PARALLEL RGB TO MIPI CSI-1 SERIAL CONVERTER Check for Samples: SN65LVDS315 FEATURES The serialized data is presented on the differential serial data output DOUT with a differential clock signal on output CLK. The frequency of CLK is 8× the DCLK input pixel clock rate.
PAGE 2
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 Table 1. Pin Description QFN Package PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL 1 GNDD 7 TXEN 13 D3 19 D7 2 DOUT– 8 MODE 14 D4 20 VS 3 DOUT+ 9 VDDA 15 D5 21 HS 4 CLK– 10 D0 16 DCLK 22 VDDIO 5 CLK+ 11 D1 17 GNDD 23 VDDD 6 GNDA 12 D2 18 D6 24 FSEL Table 2.
PAGE 4
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com FUNCTIONAL DESCRIPTION Parallel Input Port Timing Information The parallel input data must comply with the following signal timing: HS (Line Valid) DCLK Valid Image Data Blanking D[0:7] P0 P1 P2 Blanking P3 P4 P(n-1) Pn Figure 1.
PAGE 5
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 Frame Structure and Synchronization Codes Camera images are transferred in frames. Each frame contains one camera image. Each frame consists of a number of lines. A frame is always larger than the number of visible lines. The non-visible lines within a frame are called frame blanking. Frame blanking must be signaled on the SN65LVDS315 parallel input via a low VS signal.
PAGE 6
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com Preventing Wrong Synchronization To avoid actual pixel data from being erroneously interpreted as a control command, the SN65LVDS315 incorporates bit manipulation. If the SN65LVDS315 parallel input detects a bit sequence of eight 1s followed by sixteen 0s, it replaces the LSB of the 0x00 parallel input word with a one instead of a zero (so the actual pixel value will be adjusted from 0x00 to 0x01).
PAGE 7
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 Frame Structure SOF Line 1 Frame of imageCheck data (visible) EOL SOL Last visible line EOF Line blanking period The next two graphs show the construction and transmission of a frame: Frame blanking period Figure 4. Frame Structure SOF Line 1 EOL SOL Line 4 EOL SOL Line 2 EOL SOL SOF Line 1 last visible line EOL SOL Line 3 EOL EOF SOL Line 2 time Figure 5.
PAGE 8
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com VS and HS Timing to Generate the Correct Control Signals The VS and HS timing received from camera sensors varies. The SN65LVDS315 responds in the following way: CLK Frame Start and Line Start Frame start is indicated by a VS transition from low to high. The rising edge on HS following the VS high transition or occurring simultaneously with VS indicates the first valid data line and initiates the transmission of SOF.
PAGE 9
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 MODE = 1 MODE = 0 Caution: Some camera sensors generate a frame CLK sync (VS) signal that lasts longer than the HS of the last visible line. In such case, and with MODE=low, B D[0:7] P480 B B B B B B B the SN65LVDS315 transmits EOL during the last HS VS low transition and transmits EOF when VS transitions low.
PAGE 10
SN65LVDS315 Original Frame Line 1 – first visible line visible image data Line 8 - Last visible line Line blanking period SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 Frame blanking period visible image data Line 4 - Last visible line Line blanking period New Frame Line 1 – first visible line Frame blanking period www.ti.
PAGE 11
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 Following data formats are not supported by the SN65LVDS315: – RGB 444 image data – Raw Bayer 10-bit image data – Raw Bayer 6-bit image data – Raw Bayer 12-bit image data – Raw Bayer 7-bit image data – JPEG 8-bit data POWERDOWN MODES The SN65LVDS315 transmitter has two power-down modes to facilitate efficient power management. Shutdown Mode The SN65LVDS315 enters shutdown mode when the TXEN terminal is asserted low.
PAGE 12
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.
PAGE 13
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 Table 5. Mode Transition Use Cases (continued) MODE TRANSITION Acquire -> Transmit USE CASE TRANSITION SPECIFICS Device is ready to transfer data Transmit -> Standby Request transmitter to enter standby mode by stopping DCLK Transmit/Standby -> Shutdown Turn off transmitter by pulling TXEN low 1. PLL is active and approaches lock 2. PLL achieves lock within twakeup 3. Parallel data input latches into shift register. 4.
PAGE 14
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com THERMAL CHARACTERISTICS PARAMETER VALUE UNIT VDDx = 1.8 V, TA = 25°C TEST CONDITIONS fDCLK = 3.5 MHz fDCLK = 11 MHz fDCLK = 26 MHz 10.8 17.7 21.2 mW mW mW VDDx = 1.95 V, TA = –40°C fDCLK = 3.5 MHz fDCLK = 26 MHz 15.7 26.0 mW mW Typical PD Device power dissipation Maximum RECOMMENDED OPERATING CONDITIONS (1) MIN VDDIO VDDD VDDA 1.65 1.65 1.
PAGE 15
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 DEVICE ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS Supply current IDD TYP (1) MAX VDDIO = VDDD = VDDA, RL(CLK) = RL(D0) = 100 Ω, VIH=VDDIO, VIL=0V, TXEN and MODE at VDDD, typical blanking power test pattern. See Table 6 FSEL FSEL FSEL FSEL = = = = VIL, fDCLK = 3.5 MHz VIL, fDCLK = 11 MHz VIH, fDCLK = 11 MHz VIH, fDCLK = 26 MHz 4.8 7.6 5.9 9.
PAGE 16
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tr 20%-to-80% differential output signal rise fDCLK=3.
PAGE 17
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 tDS 80% VOH D[0:7], VS, HS 20% VOL tDH 80% VOH DCLK 20% VOL tF Figure 10. Input signal Setup and Hold Time Definition tDS and tDH tCLK+ CLK- CLK+ ts(DOUT) Bit(n-1) DOUT+/- th(DOUT) Bitn Figure 11. Output signal Setup and Hold Time Definition ts(DOUT) and th(DOUT) VOD tF tR 150 mV (nom) 80% 0V 20% -150 mV (nom) Figure 12.
PAGE 18
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 CLK+ DOUT+ www.ti.com R1 = 49.9 W VDx+ or VCLK+ 975 mV (nom) VDx- or VCLK- 825 mV (nom) VOD CLKDOUT- VOCM R2 = 49.9 W SN65LVDS315 C1 1 pF VOCM(PP) C2 1 pF VOCM(SS) NOTES: A. 88 MHz output test pattern on CLK output and 44 MHz output test pattern on DOUT; this is achieved by: 1. MODE = 0 2. fPCLK = 11 MHz 3. Inputs D0 ¯ = D2 ¯= D4 = D6 = VDDIO and ¯ D1 = D3 = D5¯ = D7 ¯ ¯ = GND 4.
PAGE 19
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 3 ms 2 ms <20 ns Glitch shorter than t GS will be ignored less than 20 ns Spike will be rejected Glitch shorter than t GS will be ignored TXEN tpwrup tpwrdn CLK+ tGS I CC tGS DCLK Transmitter disabled (OFF) Transmitter aquires lock; when MODE=VDD TX also detects line count for one entire frame Transmitter output remains disabled Transmitter Transmitter turns OFF disabled (OFF) Transmitter enabled (ON) Figure 16.
PAGE 20
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com Typical Blanking Power Consumption Test Pattern During blanking VS is low, and the SN65LVDS315 data output DOUT presents a high signal. The typical power consumption test patterns during the blanking time consists of one data word. The pattern repeats itself throughout the entire measurement. Table 6.
PAGE 21
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 Jitter Performance The jitter performance of the SN65LVDS315 is tested using a pattern that stresses the interconnect, particularly to test for ISI. The test pattern uses very long run lengths of consecutive bits. The pattern incorporates very high and low data rates, and maximizes switching noise. The pattern is self-repeating for the duration of the test. Table 8.
PAGE 22
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.
PAGE 23
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS (continued) SN65LVDS315 OUTPUT DATA AND CLOCK SIGNAL AT 208MBPS SN65LVDS315 OUTPUT CLOCK AND DATA A. The asymmetrical setup and hold time is optimized to meet OMAP A. Through pcb interconnect of 80-inch of FR4 at 208Mbps processor input timing. Figure 24. Figure 25.
PAGE 24
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com APPLICATION INFORMATION RECEIVER TERMINATION REQUIREMENT The SN65LVDS315 outputs two differential lanes that must be specially terminated near the CSI-1 receiver device. As shown in Figure 26, place two resistors and one capacitor in each lane (within ±20% to the values shown). There are two possible implementations, based on whether the termination inside the receiver device can be disabled.
PAGE 25
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 POWER SUPPLY DESIGN RECOMMENDATION For a multilayer PCB, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. SN65LVDS315 DECOUPLING RECOMMENDATION The SN65LVDS315 was designed to operate reliably in a constricted environment with other digital switching ICs. In cell phone designs, the SN65LVDS315 often shares a power supply with various other ICs.
PAGE 26
SN65LVDS315 SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 www.ti.com 8-Bit Camera Application Table 9. Typical Application Data Rates and Serial Lane Usage DISPLAY SCREEN RESOLUTION VISIBLE PIXEL COUNT CONTROL OVERHEAD FRAME REFRESH RATE DCLK PIXEL CLOCK FREQUENCY [MHz] DATA RATE ON D0 WITH LS=0 f(CLK) 14% 10 Hz 3.5 MHz 28 Mbps 28 MHz 38 MHz 640x480 (VGA) 307,200 640x480 (VGA) 307,200 2% 15 Hz 4.7 MHz 38 Mbps 640x480 (VGA) 307,200 10% 30 Hz 10.
PAGE 27
SN65LVDS315 www.ti.com SLLS881F – DECEMBER 2007 – REVISED SEPTEMBER 2012 REVISION HISTORY Changes from Original (December 2007) to Revision A • Page Changed the document From: Product Preview To: Production .......................................................................................... 1 Changes from Revision A (March 2008) to Revision B • Page Changed the Absoulute Maximum Ratings table - Voltage range at any input terminal value From: –0.5 to 2.175 To: –0.5 to VDDIO + 0.5V ..............
PAGE 28
PACKAGE OPTION ADDENDUM www.ti.
PAGE 29
PACKAGE OPTION ADDENDUM www.ti.
PAGE 30
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS315RGET Package Package Pins Type Drawing VQFN RGE 24 SPQ 250 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 12.4 Pack Materials-Page 1 4.25 B0 (mm) K0 (mm) P1 (mm) 4.25 1.15 8.0 W Pin1 (mm) Quadrant 12.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS315RGET VQFN RGE 24 250 210.0 185.0 35.
PAGE 32
PAGE 33
PAGE 34
PAGE 35
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.