Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - receivers LVDS 0/4 SOIC 16 N

www.ti.com

FEATURES

DESCRIPTION

GND

SN65LVDT32B

GND

D PACKAGE

(TOP VIEW)

D PACKAGE

(TOP VIEW)

SN65LVDS32B

Logic Diagram

(positive logic)

SN65LVDT32B

ONLY (4 Places)

1,2EN

GND

3,4EN

SN65LVDT3486B

D PACKAGE

(TOP VIEW)

SN65LVDS3486B

Logic Diagram

(positive logic)

SN65LVDT3486B

ONLY (4 Places)

1,2EN

3,4EN

SN65LVDT9637B

ONLY

SN65LVDT9637B

SN65LVDS9637B

Logic Diagram

(positive logic)

SN65LVDS32B , , SN65LVDT32B

SN65LVDS3486B , SN65LVDT3486B

SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

HIGH-SPEED DIFFERENTIAL RECEIVERS

• Meets or Exceeds the Requirements of ANSI

EIA/TIA-644 Standard for Signaling Rates

(1)

to 400 Mbps

• Operates With a Single 3.3-V Supply

• –2-V to 4.4-V Common-Mode Input Voltage

Range

• Differential Input Thresholds <50 mV With

50 mV of Hysteresis Over Entire Common-

Mode Input Voltage Range

• Integrated 110- Ω Line Termination Resistors

Offered With the LVDT Series

• Propagation Delay Times 4 ns (typ)

• Active Fail Safe Assures a High-Level Output

With No Input

• Bus-Pin ESD Protection Exceeds 15 kV HBM

• Inputs Remain High-Impedance on Power

Down

• Recommended Maximum Parallel Rate of

200 M-Transfer/s

• Available in Small-Outline Package With

1,27-mm Terminal Pitch

• Pin-Compatible With the AM26LS32, MC3486,

or µA9637

This family of differential line receivers offers

improved performance and features that implement

the electrical characteristics of low-voltage differential

signaling (LVDS). LVDS is defined in the

TIA/EIA-644 standard. This improved performance

represents the second generation of receiver

products for this standard, providing a better overall

solution for the cabled environment. This generation

of products is an extension to TI's overall product

portfolio and is not necessarily a replacement for

older LVDS receivers.

(1) Signaling rate, 1/t, where t is the minimum unit interval and is

expressed in the units bit/s (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

PAGE 1
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 HIGH-SPEED DIFFERENTIAL RECEIVERS FEATURES • • • • • • • • • • • • Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard for Signaling Rates (1) up to 400 Mbps Operates With a Single 3.3-V Supply –2-V to 4.
PAGE 2
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) Improved features include an input common-mode voltage range 2 V wider than the minimum required by the standard.
PAGE 3
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.
PAGE 4
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC Attenuation Network 6.5 kΩ 60 kΩ A Input 200 kΩ 3 pF 250 kΩ Attenuation Network 1 pF 6.
PAGE 5
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range (2) VCC –0.5 V to 4 V Enables or Y Voltage range –0.
PAGE 6
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) VIT1 Positive-going differential input voltage threshold VIT2 Negative-going differential input voltage threshold VIB = -2 V or 4.
PAGE 7
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.
PAGE 8
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 PARAMETER MEASUREMENT INFORMATION IIA A VO Y VID B (VIA + VIB)/2 VIA VIC IIB VO VIB Figure 1.
PAGE 9
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 PARAMETER MEASUREMENT INFORMATION (continued) VID VIA CL = 10 pF VIB VO VIA 1.4 V VIB 1V 0.4 V VID 0V –0.4 V tPHL tPLH 80% VO 20% 1.4 V VOL 20% tf A. VOH 80% tr All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, Pulsewidth = 10 ±0.2 ns .
PAGE 10
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 PARAMETER MEASUREMENT INFORMATION (continued) 1.2 V B 500 Ω A 10 pF ± VO G Inputs VTEST G 1,2,EN, or 3,4, EN NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, Pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
PAGE 11
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 Table 1. Receiver Minimum and Maximum VIT3 Input Threshold Test Voltages APPLIED VOLTAGES (1) (1) RESULTANT INPUTS VIA (mV) VIB (mV) VID (mV) VIC (mV) Output –2000 –1900 –100 –1950 L –2000 –1968 –32 –1984 H 4300 4400 –100 4350 L 4368 4400 –32 4384 H These voltages are applied for a minimum of 1.5 µs.
PAGE 12
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25°C VCC = 3.3 V TA = 25°C VOH − High-Level Output Voltage − V VOL − Low-Level Output Voltage − V 5 4 3 2 1 0 3 2 1 0 0 10 20 30 40 −40 IOL − Low-Level Output Current − mA −10 Figure 8.
PAGE 13
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREQUENCY 140 I CC − Supply Current − mA 120 VCC = 3.3 V 100 80 VCC = 3.6 V 60 VCC = 3 V 40 20 0 0 100 150 200 f − Switching Frequency − MHz Figure 11.
PAGE 14
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 APPLICATION INFORMATION 0.01 µF 1 VCC 16 0.1 µF (see Note A) 1B 100 Ω 2 3 VCC 4 5 6 1A 4B 2Y 4Y G 2A 100 Ω 7 4A 2B 3Y 3A 5V 1N645 (2 places) 15 1Y G ≈3.6 V 14 100 Ω (see Note B) 13 12 11 See Note C 10 100 Ω 8 GND 3B 9 A. Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane.
PAGE 15
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) Output Buffer Main Receiver + _ A B R Reset Failsafe Timer A > B + 80 mV + _ Failsafe B > A + 80 mV + _ Window Comparator Figure 13. Receiver With Terminated Failsafe ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER The various versions of emitter-coupled logic (i.e.
PAGE 16
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) Figure 15. LV/PECL to Remote SN65LVDS32B at 500 Mbps Receiver Output (CH1) TEST CONDITIONS • • • VCC = 3.3 V TA = 25°C (ambient temperature) All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ data.
PAGE 17
SN65LVDS32B,, SN65LVDT32B SN65LVDS3486B, SN65LVDT3486B SN65LVDS9637B, SN65LVDT9637B www.ti.com SLLS440B – OCTOBER 2000 – REVISED APRIL 2007 APPLICATION INFORMATION (continued) 100 Mbit/s 200 Mbit/s Figure 17.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.
PAGE 20
PACKAGE OPTION ADDENDUM www.ti.com 26-Mar-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS32BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS3486BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS9637BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS32BDR SOIC D 16 2500 333.2 345.9 28.6 SN65LVDS3486BDR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDS9637BDR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDS9637BDR SOIC D 8 2500 367.0 367.0 35.0 SN65LVDT32BDR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDT3486BDR SOIC D 16 2500 367.0 367.0 38.
PAGE 23
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.