Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - receivers LVDS 0/4 TSSOP 16

GND

D OR PW PACKAGE

(TOP VIEW)

D PACKAGE

(TOP VIEW)

SN65LVDS33D, SN65LVDT33D

SN65LVDS33PW, SN65LVDT33PW

logic diagram (positive logic)

SN65LVDT33 ONLY

SN65LVDT34 ONLY

logic diagram (positive logic)

SN65LVDS34D, SN65LVDT34D

SN65LVDS33, SN65LVDT33

SN65LVDS34, SN65LVDT34

www.ti.com

SLLS490B –MARCH 2001–REVISED NOVEMBER 2004

HIGH-SPEED DIFFERENTIAL RECEIVERS

Check for Samples: SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34

The high-speed switching of LVDS signals usually

FEATURES

necessitates the use of a line impedance matching

• 400-Mbps Signaling Rate

(1)

and 200-Mxfr/s

resistor at the receiving-end of the cable or

Data Transfer Rate

transmission media. The SN65LVDT series of

• Operates With a Single 3.3-V Supply

receivers eliminates this external resistor by

integrating it with the receiver. The nonterminated

• -4 V to 5 V Common-Mode Input Voltage

SN65LVDS series is also available for multidrop or

Range

other termination circuits.

• Differential Input Thresholds <±50 mV With 50

mV of Hysteresis Over Entire Common-Mode

Input Voltage Range

• Integrated 110-Ω Line Termination Resistors

On LVDT Products

• TSSOP Packaging (33 Only)

• Complies With TIA/EIA-644 (LVDS)

• Active Failsafe Assures a High-Level Output

With No Input

• Bus-Pin ESD Protection Exceeds 15 kV HBM

• Input Remains High-Impedance on Power

Down

• TTL Inputs Are 5 V Tolerant

• Pin-Compatible With the AM26LS32,

SN65LVDS32B, µA9637, SN65LVDS9637B

(1)

The signalling rate of a line, is the number of voltage

transitions that are made per second expressed in the units

bps (bits per second).

DESCRIPTION

This family of four LVDS data line receivers offers the

widest common-mode input voltage range in the

industry. These receivers provide an input voltage

range specification compatible with a 5-V PECL

signal as well as an overall increased ground-noise

tolerance. They are in industry standard footprints

with integrated termination as an option.

Precise control of the differential input voltage

thresholds allows for inclusion of 50 mV of input

voltage hysteresis to improve noise rejection on

slowly changing input signals. The input thresholds

are still no more than ±50 mV over the full input

common-mode voltage range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 HIGH-SPEED DIFFERENTIAL RECEIVERS Check for Samples: SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 FEATURES 1 • • • • • • • • • • • • (1) (1) 400-Mbps Signaling Rate and 200-Mxfr/s Data Transfer Rate Operates With a Single 3.
PAGE 2
SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC Attenuation Network Attenuation Network 1 pF 60 kΩ A Input 200 kΩ 3 pF 6.5 kΩ 250 kΩ Attenuation Network 6.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range, VCC (2) Voltage range –0.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX 2.5 4 6 ns 2.5 4 6 ns 9 ns 1.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION (continued) 1000 Ω 100 Ω 100 Ω† 1000 Ω VIC † + – VID 10 pF, 2 Places VO 10 pF Remove for testing LVDT device. VIT1 0V VID –100 mV VO 100 mV VID 0V VIT2 VO NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns. Figure 2.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VID VIA CL = 10 pF VIB VO VIA 1.4 V VIB 1V 0.4 V VID 0V −0.4 V tPHL tPLH 80% VO 20% tf A. VOH 80% 1.4 V VOL 20% tr All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulsewidth = 10 ±0.2 ns.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION (continued) 1.2 V B 500 Ω A 10 pF Inputs ± VO G VTEST G NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. VTEST 2.5 V A 1V 2V 1.4 V 0.8 V G 2V 1.4 V 0.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 www.ti.com Table 2. Receiver Minimum and Maximum VIT3 Input Threshold Test Voltages APPLIED VOLTAGES (1) (1) RESULTANT INPUTS VIA (mV) VIB (mV) VID (mV) VIC (mV) Output –4000 –3900 –100 –3950 L –4000 –3968 –32 –3984 H 4900 5000 –100 4950 L 4968 5000 –32 4984 H These voltages are applied for a minimum of 1.5 µs.
PAGE 11
SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 VCC = 3.3 V TA = 25°C VCC = 3.3 V TA = 25°C VOH − High-Level Output Voltage − V VOL − Low-Level Output Voltage − V 5 4 3 2 1 3 2 1 0 0 0 10 20 30 40 −40 −30 −20 −10 Figure 7. Figure 8.
PAGE 12
SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREQUENCY 140 120 VCC = 3.3 V I CC − Supply Current − mA 100 80 VCC = 3.6 V 60 VCC = 3 V 40 20 0 0 150 100 200 f − Switching Frequency − MHz Figure 11. APPLICATION INFORMATION 0.01 µF 1 VCC 16 0.1 µF (see Note A) 1B 100 Ω 2 3 VCC 4 5 6 1A 4B 2Y 4Y G 2A 100 Ω 7 4A 3Y 2B 3A GND 3B 5V 1N645 (2 places) 15 1Y G ≈3.
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SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 RELATED INFORMATION IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for more information.
PAGE 14
SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 www.ti.com LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at the input of the LVDS receiver.
PAGE 15
SN65LVDS33, SN65LVDT33 SN65LVDS34, SN65LVDT34 www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 EQUIPMENT • • • Tektronix PS25216 programmable power supply Tektronix HFS 9003 stimulus system Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO Tektronix PS25216 Programmable Power Supply Tektronix HFS 9003 Stimulus System Trigger Bench Test Board Tektronix TDS 784D 4-Channel Digital Phosphor Oscilloscope – DPO Figure 16. Equipment Setup 100 Mbit/s 200 Mbit/s Figure 17.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2010 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS33DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS33PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN65LVDS34DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS33DR SOIC D 16 2500 333.2 345.9 28.6 SN65LVDS33PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDS34DR SOIC D 8 2500 340.5 338.1 20.6 SN65LVDT33DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDT33PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDT34DR SOIC D 8 2500 340.5 338.1 20.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.