Datasheet

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SN65LVDS387, SN75LVDS387, SN65LVDS389

SN75LVDS389, SN65LVDS391, SN75LVDS391

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Four (’391), Eight (’389) or Sixteen (’387)

Line Drivers Meet or Exceed the

Requirements of ANSI EIA/TIA-644

Standard

Designed for Signaling Rates

†

up to

630 Mbps With Very Low Radiation (EMI)

Low-Voltage Differential Signaling With

Typical Output Voltage of 350 mV and a

100-Ω Load

Propagation Delay Times Less Than 2.9 ns

Output Skew Is Less Than 150 ps

Part-to-Part Skew Is Less Than 1.5 ns

35-mW Total Power Dissipation in Each

Driver Operating at 200 MHz

Driver Is High Impedance When Disabled or

With V

< 1.5 V

SN65’ Version Bus-Pin ESD Protection

Exceeds 15 kV

Packaged in Thin Shrink Small-Outline

Package With 20-mil Terminal Pitch

Low-Voltage TTL (LVTTL) Logic Inputs Are

5-V Tolerant

description

This family of four, eight, and sixteen differential

line drivers implements the electrical characteris-

tics of low-voltage differential signaling (LVDS).

This signaling technique lowers the output voltage

levels of 5-V differential standard levels (such as

EIA/TIA-422B) to reduce the power, increase the

switching speeds, and allow operation with a

3.3-V supply rail. Any of the sixteen current-mode

drivers will deliver a minimum differential output

voltage magnitude of 247 mV into a 100-Ω load

when enabled.

The intended application of this device and signaling technique is for point-to-point and multidrop baseband data

transmission over controlled impedance media of approximately 100 Ω. The transmission media can be

printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same

substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of

clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel

receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge

clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is

dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other

system characteristics.)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)

GND

ENA

A1A

A2A

A3A

A4A

ENB

B1A

B2A

B3A

B4A

GND

C1A

C2A

C3A

C4A

ENC

D1A

D2A

D3A

D4A

END

GND

A1Y

A1Z

A2Y

A2Z

A3Y

A3Z

A4Y

A4Z

B1Y

B1Z

B2Y

B2Z

B3Y

B3Z

B4Y

B4Z

C1Y

C1Z

C2Y

C2Z

C3Y

C3Z

C4Y

C4Z

D1Y

D1Z

D2Y

D2Z

D3Y

D3Z

D4Y

D4Z

GND

ENA

A1A

A2A

A3A

A4A

GND

B1A

B2A

B3A

B4A

ENB

GND

A1Y

A1Z

A2Y

A2Z

A3Y

A3Z

A4Y

A4Z

B1Y

B1Z

B2Y

B2Z

B3Y

B3Z

B4Y

B4Z

’LVDS389

DBT PACKAGE

(TOP VIEW)

’LVDS387

DGG PACKAGE

(TOP VIEW)

EN1,2

GND

EN3,4

’LVDS391

D OR PW PACKAGE

(TOP VIEW)

Summary of content (20 pages)

PAGE 1
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 D D D D D D D D D D D Four (’391), Eight (’389) or Sixteen (’387) Line Drivers Meet or Exceed the Requirements of ANSI EIA / TIA-644 Standard Designed for Signaling Rates† up to 630 Mbps With Very Low Radiation (EMI) Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load Propagation Delay Times Less Than 2.
PAGE 2
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 description (continued) When disabled, the driver outputs are high impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open circuited. The SN65LVDS387, SN65LVDS389, and SN65LVDS391 are characterized for operation from –40°C to 85°C.
PAGE 3
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 equivalent input and output schematic diagrams EQUIVALENT OF EACH A OR EN INPUT VCC TYPICAL OF ALL OUTPUTS VCC 50 Ω A or EN Input 10 kΩ 5Ω Y or Z Output 7V 300 kΩ 7V absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS |VOD| Differential output voltage magnitude ∆|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ∆VOC(SS) Change in steady-state common-mode output voltage b
PAGE 5
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION IOY Y II A VOD IOZ Z VOY GND VI VOC VOZ (VOY + VOZ)/2 Figure 1. Voltage and Current Definitions 3.75 kΩ Y 100 Ω 3.75 kΩ VOD Input Z ± 0 V ≤ VTEST ≤ 2.4 V Figure 2. VOD Test Circuit Y 49.
PAGE 6
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 PARAMETER MEASUREMENT INFORMATION 49.9 Ω ± 1% (2 Places) Y 0.8 V or 2 V Z + Input CL = 10 pF (2 Places) VOY 1.2 V – 2V 1.4 V 0.8 V Input VOY or VOZ VOZ tPZH tPHZ ≅ 1.4 V 1.3 V 1.2 V tPZL tPLZ 1.2 V VOZ 1.
PAGE 7
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 TYPICAL CHARACTERISTICS ’LVDS391 SUPPLY CURRENT (RMS) vs SWITCHING FREQUENCY 60 All outputs loaded and enabled. I CC – Supply Current – mA 50 VCC = 3.6 V 40 30 VCC = 3.
PAGE 8
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 TYPICAL CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.1 t PHL – High-To-Low Propagation Delay Time – ns t PLH – Low-To-High Propagation Delay Time – ns LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.0 VCC = 3.6 V 1.9 1.8 1.7 VCC = 3 V 1.6 VCC = 3.3 V 1.5 1.4 1.3 –40 –20 0 20 40 60 80 100 2.
PAGE 9
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs TIME VOY VO – Output Voltage – V VOZ VOD t – Time – ns Figure 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
PAGE 10
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 APPLICATION INFORMATION Host Host Controller Power Balanced Interconnect Power Target T DBn DBn Target Controller T DBn–1 DBn–1 T DBn–2 DBn–2 T DBn–3 DBn–3 T DB2 DB2 T DB1 DB1 T DB0 DB0 T TX Clock RX Clock SN65LVDS387 or 389 LVDS Receiver(s) Indicates twisting of the conductors. Indicates the line termination T circuit.
PAGE 11
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 APPLICATION INFORMATION height abs . jitter width unit interval Figure 15. Typical LVDS Eyepattern A generally accepted range of jitter at the receiver inputs that allows data recovery is 5% to 20% of the unit interval (data pulse width).
PAGE 12
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.
PAGE 13
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 MECHANICAL DATA DBT (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 30 PINS SHOWN 0,50 0,27 0,17 30 16 0,08 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 15 0°– 8° 0,75 0,50 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 28 30 38 44 50 A MAX 7,90 7,90 9,80 11,10 12,60 A MIN 7,70 7,70 9,60 10,90 12,40 DIM 4073252/D 09
PAGE 14
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 MECHANICAL DATA DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D.
PAGE 15
SN65LVDS387, SN75LVDS387, SN65LVDS389 SN75LVDS389, SN65LVDS391, SN75LVDS391 HIGH-SPEED DIFFERENTIAL LINE DRIVERS SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001 MECHANICAL DATA PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 404006
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS387DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1 SN65LVDS389DBTR TSSOP DBT 38 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1 SN65LVDS391DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 25-Sep-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS387DGGR TSSOP DGG 64 2000 346.0 346.0 41.0 SN65LVDS389DBTR TSSOP DBT 38 2000 346.0 346.0 33.0 SN65LVDS391DR SOIC D 16 2500 346.0 346.0 33.0 SN65LVDS391PWR TSSOP PW 16 2000 346.0 346.0 29.0 SN75LVDS387DGGR TSSOP DGG 64 2000 346.0 346.0 41.0 SN75LVDS389DBTR TSSOP DBT 38 2000 346.0 346.
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