Datasheet
1
FEATURES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D4
V
CC
D5
D6
GND
D7
D8
V
CC
D9
D10
GND
D11
D12
NC
D13
D14
GND
D15
D16
D17
V
CC
D18
D19
GND
D3
D2
GND
D1
D0
NC
LVDSGND
Y0M
Y0P
Y1M
Y1P
LVDSV
CC
LVDSGND
Y2M
Y2P
CLKOUTM
CLKOUTP
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKIN
D20
DGG PACKAGE
(TOP VIEW)
NC − Not Connected
DESCRIPTION/ORDERING INFORMATION
SN65LVDS84AQ-Q1
www.ti.com
........................................................................................................................................................ SLLS766A – AUGUST 2006 – REVISED APRIL 2008
FlatLink™ TRANSMITTER
2
• 21:3 Data Channel Compression at up to
196 Mbytes/s Throughput
• Suited for SVGA, XGA, or SXGA Data
Transmission From Controller to Display With
Very Low EMI
• 21 Data Channels Plus Clock In Low-Voltage
TTL Inputs and 3 Data Channels Plus Clock
Out Low-Voltage Differential Signaling (LVDS)
Outputs
• Operates From a Single 3.3-V Supply and
89 mW (Typ)
• Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch
• Consumes Less Than 0.54 mW When Disabled
• Wide Phase-Lock Input Frequency Range:
31 MHz to 75 MHz
• No External Components Required for PLL
• Outputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
• SSC Tracking Capability of 3% Center Spread
at 50-kHz Modulation Frequency
• Improved Replacement for SN75LVDS84 and
NSC DS90CF363A 3-V Device
• Qualified for Automotive Applications
The SN65LVDS84AQ FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, and four
low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of
single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a
compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.
When transmitting, data bits D0 – D20 are each loaded into registers of the SN65LVDS84AQ upon the falling
edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices.
The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The
frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS84AQ requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The
only user intervention is the possible use of the shutdown/clear ( SHTDN) active-low input to inhibit the clock and
shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal
registers to a low level.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 FlatLink is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 – 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.