Datasheet

CLKIN
EVEN Dn
ODD Dn
T
V
IH
= 2 V and V
IL
= 0.8 V
CLKIN
V
OD(H)
0 V
t
7
t
0
t
6
t
5
t
4
t
3
t
2
t
1
V
OD(L)
1.4 V
t
7
t
0
–t
6
CLKOUT
Yn
CLKIN
CLKOUT
or Xn
SN65LVDS95
SLLS297J –MAY 1998– REVISED MAY 2011 www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
(1) The worst-case test pattern produces nearly the maximum switching frequency for all of the LV-TTL outputs.
Figure 4. Worst-Case Power Test Pattern
Figure 5. Timing Definitions
8 Copyright © 1998–2011, Texas Instruments Incorporated