Datasheet

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FEATURES

DESCRIPTION

192013 2

1312119 10

GND

SN55LVDS32FK

(TOP VIEW)

GND

SN55LVDS32 . . . J OR W

SN65LVDS32 . . . D OR PW

(Marked as LVDS32 or 65LVDS32)

(TOP VIEW)

1,2EN

GND

3,4EN

SN65LVDS3486D (Marked as LVDS3486)

(TOP VIEW)

GND

SN65LVDS9637D (Marked as DK637 or LVDS37)

SN65LVDS9637DGN (Marked as L37)

SN65LVDS9637DGK (Marked as AXF)

(TOP VIEW)

SN55LVDS32 , SN65LVDS32

SN65LVDS3486 , SN65LVDS9637

SLLS262Q – JULY 1997 – REVISED JULY 2007

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

• Meet or Exceed the Requirements of ANSI

TIA/EIA-644 Standard

• Operate With a Single 3.3-V Supply

• Designed for Signaling Rates of up to 100

Mbps (See Table 1 )

• Differential Input Thresholds ± 100 mV Max

• Typical Propagation Delay Time of 2.1 ns

• Power Dissipation 60 mW Typical Per

Receiver at Maximum Data Rate

• Bus-Terminal ESD Protection Exceeds 8 kV

• Low-Voltage TTL (LVTTL) Logic Output Levels

• Pin Compatible With AM26LS32, MC3486, and

μ A9637

• Open-Circuit Fail-Safe

• Cold Sparing for Space and High Reliability

Applications Requiring Redundancy

The SN55LVDS32, SN65LVDS32, SN65LVDS3486,

and SN65LVDS9637 are differential line receivers

that implement the electrical characteristics of

low-voltage differential signaling (LVDS). This

signaling technique lowers the output voltage levels

of 5-V differential standard levels (such as

EIA/TIA-422B) to reduce the power, increase the

switching speeds, and allow operation with a 3.3-V

supply rail. Any of the four differential receivers

provides a valid logical output state with a ± 100-mV

differential input voltage within the input

common-mode voltage range. The input

common-mode voltage range allows 1 V of ground

potential difference between two LVDS nodes.

The intended application of these devices and

signaling technique is both point-to-point and

multidrop (one driver and multiple receivers) data

transmission over controlled impedance media of

approximately 100 Ω . The transmission media may

be printed-circuit board traces, backplanes, or

cables. The ultimate rate and distance ofdata

transfer depends on the attenuation characteristics of

the media and the noise coupling to the environment.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

PAGE 1
SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are characterized for operation from –40°C to 85°C. The SN55LVDS32 is characterized for operation from –55°C to 125°C. Table 1.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 logic symbol† SN65LVDS9637 1A 1B 2A 2B † 8 2 7 6 3 5 1Y 2Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING (1) (2) D (8) 725 mW 5.8 mW/°C 464 mW 377 mW — D (16) 950 mW 7.6 mW/°C 608 mW 494 mW — — DGK 425 mW 3.4 mW/°C 272 mW 221 mW DGN (2) 2.14 W 17.1 mW/°C 1.37 W 1.11 W — FK 1375 mW 11.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION A Y VID B (VIA + VIB)/2 VIA VIC VO VIB Figure 2. Voltage Definitions Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages 8 Resulting Differential Input Voltage Resulting Common-Mode Input Voltage VIA(V) VIB(V) VID(mV) VIC(V) 1.25 1.15 100 1.2 1.15 1.25 –100 1.2 2.4 2.3 100 2.35 2.3 2.4 –100 2.35 0.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 VID VIA CL = 10 pF VIB VO VIA 1.4 V VIB 1V VID 0.4 V 0 -0.4 V tPHL tPLH 80% VO 20% VOH 80% 1.4 V VOL 20% tf tr A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 3.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 B 1.2 V 500 Ω A Inputs (see Note A) G 10 pF (see Note B) ± VO VTEST G 1,2EN or 3,4EN VTEST 2.5 V A 1V 2V 1.4 V 0.8 V G, 1,2EN, or 3,4EN 2V 1.4 V 0.8 V G tPLZ tPZL tPLZ tPZL Y VTEST 0 1.4 V A 2V 1.4 V 0.8 V 2V 1.4 V 0.8 V G, 1,2EN, or 3,4EN G tPHZ tPZH 2.5 V 1.4 V VOL + 0.5 V VOL tPHZ tPZH Y VOH VOH - 0.5 V 1.4 V 0 A.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 TYPICAL CHARACTERISTICS SN55LVDS32, SN65LVDS32 SUPPLY CURRENT vs FREQUENCY LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE Four Receivers, Loaded Per Figure 3, Switching Simultaneously VCC = 3.6 V VCC = 3.3 V 65 VCC = 3 V 55 45 35 25 15 50 100 150 200 2.7 2.5 VCC = 3 V VCC = 3.3 V 2.3 VCC = 3.6 V 2.1 1.9 1.7 1.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 TYPICAL CHARACTERISTICS (continued) HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 3.5 5.0 2.5 2.0 1.5 1.0 0.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 −60 12 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V 4.5 3.0 0.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 APPLICATION INFORMATION Equipment • • • Hewlett Packard HP6624A DC power supply Tektronix TDS7404 Real Time Scope Agilent ParBERT E4832A Hewlett Packard HP6624A DC Power Supply Agilent ParBERT (E4832A) Bench Test Board Tektronix TDS7404 Real Time Scope Figure 10. Equipment Setup All Rx running at 100 Mbps; Channel 1: 1Y, Channel 2: 2Y; Channel 3: 3Y; Channel 4: 4Y Figure 11.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 APPLICATION INFORMATION (continued) All Rx running at 100 Mbps; Channel 1: 1Y, Channel 2: 2Y; Channel 3: 3Y; Channel 4: 4Y Figure 12. Typical Eye Patterns SN65LVDS3486: (T = 25°C; VCC = 3.6 V; PRBS = 223-1) All Rx running at 150 Mbps; Channel 1: 1Y, Channel 2: 2Y Figure 13. Typical Eye Patterns SN65LVDS9637: (T = 25°C; VCC = 3.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 APPLICATION INFORMATION (continued) USING AN LVDS RECEIVER WITH RS-422 DATA Receipt of data from a TIA/EIA-422 line driver can be accomplished using a TIA/EIA-644 line receiver with the addition of an attenuator circuit. This technique gives the user a high-speed and low-power 422 receiver.
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SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 APPLICATION INFORMATION (continued) TRANSMISSION DISTANCE vs SIGNALING RATE Transmission Distance − m 100 30% Jitter (see Note A) 10 5% Jitter (see Note A) 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 10 100 1000 Signaling Rate − Mbps A. This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern. Figure 15.
PAGE 17
SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 APPLICATION INFORMATION 1/4 ’LVDS31 Strb/Data_TX TpBias on Twisted-Pair A Strb/Data_Enable TP 55 Ω ’LVDS32 5 kΩ Data/Strobe 55 Ω 3.3 V TP 20 kΩ 500 Ω VG on Twisted-Pair B 1 Arb_RX 500 Ω 20 kΩ 3.3 V 500 Ω 20 kΩ 2 Arb_RX 500 Ω 20 kΩ 3.3 V 7 kΩ Twisted-Pair B Only 7 kΩ 10 kΩ Port_Status 3.3 kΩ A. Resistors are leadless, thick film (0603), 5% tolerance. B.
PAGE 18
SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 APPLICATION INFORMATION (continued) Open-input circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors (see Figure 18).
PAGE 19
SN55LVDS32, SN65LVDS32 SN65LVDS3486, SN65LVDS9637 www.ti.com SLLS262Q – JULY 1997 – REVISED JULY 2007 APPLICATION INFORMATION (continued) COLD SPARING Systems using cold sparing have a redundant device electrically connected without power supplied. To support this configuration, the spare must present a high-input impedance to the system so that it does not draw appreciable power. In cold sparing, voltage may be applied to an I/O before and during power up of a device.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Sep-2013 Status (1) SNJ55LVDS32W ACTIVE Package Type Package Pins Package Drawing Qty CFP W 16 1 Eco Plan Lead/Ball Finish (2) TBD MSL Peak Temp Op Temp (°C) Device Marking (3) A42 N / A for Pkg Type (4/5) -55 to 125 5962-9762201QF A SNJ55LVDS32W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65LVDS32DR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN65LVDS32NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN65LVDS32PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS32DR SOIC D 16 2500 333.2 345.9 28.6 SN65LVDS32NSR SO NS 16 2000 367.0 367.0 38.0 SN65LVDS32PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN65LVDS3486DR SOIC D 16 2500 367.0 367.0 38.0 SN65LVDS9637DGKR VSSOP DGK 8 2500 358.0 335.0 35.0 SN65LVDS9637DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.